Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	768	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	6345	1			T17	14		T18	20		T19	21
len_601_800	14230	1			T17	13		T18	38		T19	39
len_401_600	9319	1			T17	14		T18	20		T19	30
len_201_400	17041	1			T14	251		T17	9		T18	5
len_65_200	75089	1			T14	680		T17	2		T18	2
len_min_for_xof_require_squeeze	999	1			T14	10		T30	2		T46	9
len_keccak_block_sizes[72]	770	1			T14	5		T46	9		T27	2
len_keccak_block_sizes[104]	776	1			T14	5		T17	1		T46	9
len_keccak_block_sizes[136]	781	1			T14	5		T46	9		T170	1
len_keccak_block_sizes[144]	291	1			T14	5		T27	2		T171	1
len_keccak_block_sizes[168]	307	1			T14	5		T170	1		T172	5
len_datapath_width	14499	1			T4	3		T5	3		T6	3
len_2_63	216842	1			T4	6		T5	6		T6	6
len_1	68	1			T31	1		T52	1		T28	1