Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11610825 |
1 |
|
|
T4 |
96 |
|
T5 |
96 |
|
T6 |
96 |
auto[1] |
27067827 |
1 |
|
|
T4 |
450 |
|
T5 |
450 |
|
T6 |
450 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
38554624 |
1 |
|
|
T4 |
546 |
|
T5 |
546 |
|
T6 |
546 |
triple_byte_access |
41239 |
1 |
|
|
T14 |
310 |
|
T17 |
17 |
|
T18 |
22 |
halfword_access |
41467 |
1 |
|
|
T14 |
316 |
|
T17 |
18 |
|
T18 |
19 |
byte_access |
41322 |
1 |
|
|
T14 |
310 |
|
T17 |
14 |
|
T18 |
24 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
11486797 |
1 |
|
|
T4 |
96 |
|
T5 |
96 |
|
T6 |
96 |
auto[0] |
triple_byte_access |
41239 |
1 |
|
|
T14 |
310 |
|
T17 |
17 |
|
T18 |
22 |
auto[0] |
halfword_access |
41467 |
1 |
|
|
T14 |
316 |
|
T17 |
18 |
|
T18 |
19 |
auto[0] |
byte_access |
41322 |
1 |
|
|
T14 |
310 |
|
T17 |
14 |
|
T18 |
24 |
auto[1] |
word_access |
27067827 |
1 |
|
|
T4 |
450 |
|
T5 |
450 |
|
T6 |
450 |