Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 272 1 T63 7 T65 4 T66 4
all_values[1] 272 1 T63 7 T65 4 T66 4
all_values[2] 272 1 T63 7 T65 4 T66 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 455 1 T63 17 T65 5 T66 6
auto[1] 361 1 T63 4 T65 7 T66 6


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 322 1 T63 9 T65 6 T67 11
auto[1] 494 1 T63 12 T65 6 T66 12


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 481 1 T63 13 T65 9 T66 7
auto[1] 335 1 T63 8 T65 3 T66 5


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 58 1 T63 2 T67 3 T156 2
all_values[0] auto[0] auto[0] auto[1] 32 1 T63 1 T66 1 T67 1
all_values[0] auto[0] auto[1] auto[0] 46 1 T65 1 T67 1 T157 3
all_values[0] auto[0] auto[1] auto[1] 26 1 T63 1 T65 1 T66 2
all_values[0] auto[1] auto[0] auto[1] 76 1 T63 2 T65 2 T66 1
all_values[0] auto[1] auto[1] auto[1] 34 1 T63 1 T67 1 T156 1
all_values[1] auto[0] auto[0] auto[0] 56 1 T63 1 T65 2 T67 2
all_values[1] auto[0] auto[0] auto[1] 33 1 T63 2 T157 1 T158 2
all_values[1] auto[0] auto[1] auto[0] 53 1 T63 2 T65 2 T67 3
all_values[1] auto[0] auto[1] auto[1] 18 1 T66 2 T67 1 T157 2
all_values[1] auto[1] auto[0] auto[1] 61 1 T63 2 T66 2 T67 1
all_values[1] auto[1] auto[1] auto[1] 51 1 T156 2 T157 2 T159 1
all_values[2] auto[0] auto[0] auto[0] 59 1 T63 4 T67 1 T156 1
all_values[2] auto[0] auto[0] auto[1] 21 1 T67 1 T156 2 T159 1
all_values[2] auto[0] auto[1] auto[0] 50 1 T65 1 T67 1 T156 2
all_values[2] auto[0] auto[1] auto[1] 29 1 T65 2 T66 2 T67 1
all_values[2] auto[1] auto[0] auto[1] 59 1 T63 3 T65 1 T66 2
all_values[2] auto[1] auto[1] auto[1] 54 1 T67 2 T156 1 T159 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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