Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100757034	1			T2	3123		T3	11784		T12	457315
all_values[1]	100757034	1			T2	3123		T3	11784		T12	457315
all_values[2]	100757034	1			T2	3123		T3	11784		T12	457315

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

605040

1

T2

252

T3

344

T12

6

auto[1]

301666062

1

T2

9117

T3

35008

T12

137193

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300737058

1

T2

9273

T3

34989

T12

136168

auto[1]

1534044

1

T2

96

T3

363

T12

10257

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	198180	1			T13	119		T14	18		T66	1
all_values[0]	auto[0]	auto[1]	2191	1			T13	2		T14	14		T66	2
all_values[0]	auto[1]	auto[0]	100047506	1			T2	3091		T3	11663		T12	453896
all_values[0]	auto[1]	auto[1]	509157	1			T2	32		T3	121		T12	3419
all_values[1]	auto[0]	auto[0]	201742	1			T2	1		T12	2		T14	10
all_values[1]	auto[0]	auto[1]	1714	1			T12	1		T14	8		T15	1
all_values[1]	auto[1]	auto[0]	100043944	1			T2	3090		T3	11663		T12	453894
all_values[1]	auto[1]	auto[1]	509634	1			T2	32		T3	121		T12	3418
all_values[2]	auto[0]	auto[0]	199568	1			T2	249		T3	343		T12	2
all_values[2]	auto[0]	auto[1]	1645	1			T2	2		T3	1		T12	1
all_values[2]	auto[1]	auto[0]	100046118	1			T2	2842		T3	11320		T12	453894
all_values[2]	auto[1]	auto[1]	509703	1			T2	30		T3	120		T12	3418