Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
324536 |
1 |
|
|
T2 |
2 |
|
T3 |
170 |
|
T12 |
4530 |
auto[1] |
370702 |
1 |
|
|
T2 |
60 |
|
T14 |
4528 |
|
T15 |
140 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174960 |
1 |
|
|
T2 |
10 |
|
T3 |
42 |
|
T12 |
1130 |
lower_val |
171650 |
1 |
|
|
T2 |
22 |
|
T3 |
29 |
|
T12 |
1118 |
zero_val |
1954 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T12 |
5 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
346744 |
1 |
|
|
T2 |
30 |
|
T3 |
94 |
|
T12 |
2282 |
lower_val |
348476 |
1 |
|
|
T2 |
32 |
|
T3 |
76 |
|
T12 |
2248 |
zero_val |
18 |
1 |
|
|
T115 |
2 |
|
T75 |
2 |
|
T150 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
40796 |
1 |
|
|
T3 |
24 |
|
T12 |
577 |
|
T13 |
8 |
higher_val |
higher_val |
auto[1] |
46654 |
1 |
|
|
T2 |
4 |
|
T14 |
556 |
|
T15 |
16 |
higher_val |
lower_val |
auto[0] |
40412 |
1 |
|
|
T3 |
18 |
|
T12 |
553 |
|
T13 |
18 |
higher_val |
lower_val |
auto[1] |
47092 |
1 |
|
|
T2 |
6 |
|
T14 |
540 |
|
T15 |
12 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T151 |
2 |
|
T152 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T75 |
2 |
|
T153 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
39898 |
1 |
|
|
T3 |
16 |
|
T12 |
582 |
|
T13 |
11 |
lower_val |
higher_val |
auto[1] |
45397 |
1 |
|
|
T2 |
12 |
|
T14 |
537 |
|
T15 |
24 |
lower_val |
lower_val |
auto[0] |
40158 |
1 |
|
|
T3 |
13 |
|
T12 |
536 |
|
T13 |
6 |
lower_val |
lower_val |
auto[1] |
46193 |
1 |
|
|
T2 |
10 |
|
T14 |
572 |
|
T15 |
21 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T115 |
1 |
|
T152 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T150 |
1 |
|
T153 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
700 |
1 |
|
|
T3 |
1 |
|
T12 |
2 |
|
T14 |
1 |
zero_val |
higher_val |
auto[1] |
271 |
1 |
|
|
T14 |
6 |
|
T25 |
4 |
|
T37 |
1 |
zero_val |
lower_val |
auto[0] |
706 |
1 |
|
|
T2 |
1 |
|
T12 |
3 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
277 |
1 |
|
|
T14 |
4 |
|
T65 |
2 |
|
T37 |
1 |