Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100757034	1			T2	3123		T3	11784		T12	457315
all_pins[1]	100757034	1			T2	3123		T3	11784		T12	457315
all_pins[2]	100757034	1			T2	3123		T3	11784		T12	457315

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	243481885	1			T2	7924		T3	30004		T12	115427
values[0x1]	58789217	1			T2	1445		T3	5348		T12	217671
transitions[0x0=>0x1]	58322908	1			T2	1419		T3	5237		T12	216332
transitions[0x1=>0x0]	58322932	1			T2	1419		T3	5237		T12	216332

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100247877	1			T2	3091		T3	11663		T12	453896
all_pins[0]	values[0x1]	509157	1			T2	32		T3	121		T12	3419
all_pins[0]	transitions[0x0=>0x1]	219974	1			T2	6		T3	10		T12	2080
all_pins[0]	transitions[0x1=>0x0]	57635762	1			T2	1387		T3	4444		T12	212913
all_pins[1]	values[0x0]	42832089	1			T2	1710		T3	7229		T12	243063
all_pins[1]	values[0x1]	57924945	1			T2	1413		T3	4555		T12	214252
all_pins[1]	transitions[0x0=>0x1]	57749982	1			T2	1413		T3	4555		T12	214252
all_pins[1]	transitions[0x1=>0x0]	180152	1			T3	672		T15	456		T17	194
all_pins[2]	values[0x0]	100401919	1			T2	3123		T3	11112		T12	457315
all_pins[2]	values[0x1]	355115	1			T3	672		T15	456		T17	195
all_pins[2]	transitions[0x0=>0x1]	352952	1			T3	672		T15	456		T17	195
all_pins[2]	transitions[0x1=>0x0]	507018	1			T2	32		T3	121		T12	3419