Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	634	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5489	1			T2	1		T3	7		T13	5
len_601_800	12580	1			T2	9		T3	26		T13	15
len_401_600	8449	1			T2	4		T3	19		T13	8
len_201_400	16495	1			T2	4		T3	6		T12	251
len_65_200	73850	1			T3	1		T12	680		T13	5
len_min_for_xof_require_squeeze	1008	1			T12	10		T14	10		T18	9
len_keccak_block_sizes[72]	744	1			T12	5		T14	5		T18	9
len_keccak_block_sizes[104]	750	1			T12	5		T14	5		T18	9
len_keccak_block_sizes[136]	747	1			T12	5		T14	5		T18	9
len_keccak_block_sizes[144]	281	1			T12	5		T14	5		T175	5
len_keccak_block_sizes[168]	289	1			T12	5		T14	5		T26	1
len_datapath_width	14213	1			T12	5		T14	5		T18	9
len_2_63	214796	1			T2	13		T3	1		T12	1329
len_1	70	1			T27	2		T176	1		T177	1