Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 266 1 T99 4 T100 4 T101 7
all_values[1] 266 1 T99 4 T100 4 T101 7
all_values[2] 266 1 T99 4 T100 4 T101 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 418 1 T99 9 T100 5 T101 13
auto[1] 380 1 T99 3 T100 7 T101 8


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 328 1 T99 6 T100 5 T101 9
auto[1] 470 1 T99 6 T100 7 T101 12


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 481 1 T99 7 T100 6 T101 12
auto[1] 317 1 T99 5 T100 6 T101 9


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 59 1 T99 1 T100 2 T101 2
all_values[0] auto[0] auto[0] auto[1] 22 1 T101 1 T161 2 T162 1
all_values[0] auto[0] auto[1] auto[0] 62 1 T99 1 T100 2 T163 2
all_values[0] auto[0] auto[1] auto[1] 26 1 T164 1 T165 2 T166 2
all_values[0] auto[1] auto[0] auto[1] 49 1 T99 1 T101 4 T167 1
all_values[0] auto[1] auto[1] auto[1] 48 1 T99 1 T163 1 T168 1
all_values[1] auto[0] auto[0] auto[0] 74 1 T99 2 T101 1 T167 1
all_values[1] auto[0] auto[0] auto[1] 28 1 T99 1 T163 2 T169 2
all_values[1] auto[0] auto[1] auto[0] 35 1 T100 1 T101 3 T163 1
all_values[1] auto[0] auto[1] auto[1] 18 1 T167 1 T164 1 T142 1
all_values[1] auto[1] auto[0] auto[1] 60 1 T99 1 T100 2 T101 2
all_values[1] auto[1] auto[1] auto[1] 51 1 T100 1 T101 1 T167 1
all_values[2] auto[0] auto[0] auto[0] 47 1 T99 1 T101 1 T167 1
all_values[2] auto[0] auto[0] auto[1] 24 1 T101 1 T164 1 T142 2
all_values[2] auto[0] auto[1] auto[0] 51 1 T99 1 T101 2 T163 3
all_values[2] auto[0] auto[1] auto[1] 35 1 T100 1 T101 1 T167 1
all_values[2] auto[1] auto[0] auto[1] 55 1 T99 2 T100 1 T101 1
all_values[2] auto[1] auto[1] auto[1] 54 1 T100 2 T101 1 T167 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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