Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100545703	1			T1	72		T3	160897		T9	265
all_values[1]	100545703	1			T1	72		T3	160897		T9	265
all_values[2]	100545703	1			T1	72		T3	160897		T9	265

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

634685

1

T1

89

T3

11

T9

13

auto[1]

301002424

1

T1

127

T3

482680

T9

782

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300099528

1

T1

201

T3

481311

T9

759

auto[1]

1537581

1

T1

15

T3

1380

T9

36

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	228285	1			T1	55		T17	285		T18	110
all_values[0]	auto[0]	auto[1]	2120	1			T1	4		T17	2		T18	2
all_values[0]	auto[1]	auto[0]	99804891	1			T1	12		T3	160437		T9	253
all_values[0]	auto[1]	auto[1]	510407	1			T1	1		T3	460		T9	12
all_values[1]	auto[0]	auto[0]	176634	1			T1	28		T3	7		T4	11
all_values[1]	auto[0]	auto[1]	1490	1			T1	2		T3	4		T13	3
all_values[1]	auto[1]	auto[0]	99856542	1			T1	39		T3	160430		T9	253
all_values[1]	auto[1]	auto[1]	511037	1			T1	3		T3	456		T9	12
all_values[2]	auto[0]	auto[0]	224655	1			T9	10		T5	34		T13	3871
all_values[2]	auto[0]	auto[1]	1501	1			T9	3		T5	2		T13	3
all_values[2]	auto[1]	auto[0]	99808521	1			T1	67		T3	160437		T9	243
all_values[2]	auto[1]	auto[1]	511026	1			T1	5		T3	460		T9	9