Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
353074 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
620 |
auto[1] |
344804 |
1 |
|
|
T1 |
4 |
|
T14 |
618 |
|
T15 |
4528 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
175019 |
1 |
|
|
T3 |
158 |
|
T9 |
4 |
|
T5 |
2 |
lower_val |
172869 |
1 |
|
|
T1 |
3 |
|
T3 |
132 |
|
T9 |
8 |
zero_val |
1883 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
348826 |
1 |
|
|
T1 |
4 |
|
T3 |
350 |
|
T9 |
16 |
lower_val |
349032 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
270 |
zero_val |
20 |
1 |
|
|
T143 |
2 |
|
T167 |
2 |
|
T168 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
44217 |
1 |
|
|
T3 |
94 |
|
T9 |
3 |
|
T5 |
1 |
higher_val |
higher_val |
auto[1] |
43371 |
1 |
|
|
T14 |
89 |
|
T15 |
551 |
|
T18 |
47 |
higher_val |
lower_val |
auto[0] |
44243 |
1 |
|
|
T3 |
64 |
|
T9 |
1 |
|
T5 |
1 |
higher_val |
lower_val |
auto[1] |
43180 |
1 |
|
|
T14 |
75 |
|
T15 |
587 |
|
T18 |
38 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T169 |
2 |
|
T170 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
5 |
1 |
|
|
T143 |
1 |
|
T168 |
1 |
|
T171 |
1 |
lower_val |
higher_val |
auto[0] |
43783 |
1 |
|
|
T3 |
82 |
|
T9 |
7 |
|
T5 |
6 |
lower_val |
higher_val |
auto[1] |
42595 |
1 |
|
|
T1 |
3 |
|
T14 |
64 |
|
T15 |
568 |
lower_val |
lower_val |
auto[0] |
43906 |
1 |
|
|
T3 |
50 |
|
T9 |
1 |
|
T4 |
1 |
lower_val |
lower_val |
auto[1] |
42583 |
1 |
|
|
T14 |
88 |
|
T15 |
567 |
|
T18 |
31 |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T168 |
1 |
|
T172 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
709 |
1 |
|
|
T3 |
1 |
|
T9 |
1 |
|
T13 |
4 |
zero_val |
higher_val |
auto[1] |
264 |
1 |
|
|
T15 |
4 |
|
T18 |
1 |
|
T121 |
1 |
zero_val |
lower_val |
auto[0] |
680 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
zero_val |
lower_val |
auto[1] |
230 |
1 |
|
|
T18 |
1 |
|
T121 |
1 |
|
T128 |
3 |