Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10352	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8909	1			T3	24		T13	21		T14	24
len_5001_7500	14436	1			T1	2		T3	24		T13	57
len_2501_5000	9311	1			T1	1		T3	24		T13	18
len_1025_2500	5413	1			T3	14		T13	8		T14	14
len_769_1024	6428	1			T3	2		T5	3		T13	1
len_513_768	6785	1			T3	3		T5	1		T13	1
len_257_512	21239	1			T3	2		T5	2		T13	1
len_0_256	258854	1			T3	211		T9	9		T5	2
len_keccak_block_sizes[72]	724	1			T3	2		T14	2		T15	3
len_keccak_block_sizes[104]	625	1			T3	2		T14	2		T15	3
len_keccak_block_sizes[136]	526	1			T15	3		T95	2		T92	2
len_keccak_block_sizes[144]	417	1			T15	3		T92	2		T93	2
len_keccak_block_sizes[168]	326	1			T15	3		T78	3		T28	1
len_1	753	1			T3	2		T14	2		T15	3
len_0	1224	1			T3	2		T13	1		T14	2