Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100545703	1			T1	72		T3	160897		T9	265
all_pins[1]	100545703	1			T1	72		T3	160897		T9	265
all_pins[2]	100545703	1			T1	72		T3	160897		T9	265

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	241968140	1			T1	197		T3	406502		T9	619
values[0x1]	59668969	1			T1	19		T3	76189		T9	176
transitions[0x0=>0x1]	59240341	1			T1	18		T3	75790		T9	164
transitions[0x1=>0x0]	59240360	1			T1	18		T3	75790		T9	164

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100035296	1			T1	71		T3	160437		T9	253
all_pins[0]	values[0x1]	510407	1			T1	1		T3	460		T9	12
all_pins[0]	transitions[0x0=>0x1]	219674	1			T3	61		T13	26		T14	59
all_pins[0]	transitions[0x1=>0x0]	58556702	1			T1	17		T3	75330		T9	152
all_pins[1]	values[0x0]	41698268	1			T1	54		T3	85168		T9	101
all_pins[1]	values[0x1]	58847435	1			T1	18		T3	75729		T9	164
all_pins[1]	transitions[0x0=>0x1]	58711439	1			T1	18		T3	75729		T9	164
all_pins[1]	transitions[0x1=>0x0]	175131	1			T61	9		T62	104		T31	1190
all_pins[2]	values[0x0]	100234576	1			T1	72		T3	160897		T9	265
all_pins[2]	values[0x1]	311127	1			T61	9		T62	104		T31	1193
all_pins[2]	transitions[0x0=>0x1]	309228	1			T61	9		T62	103		T31	1193
all_pins[2]	transitions[0x1=>0x0]	508527	1			T1	1		T3	460		T9	12