Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	641	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5616	1			T5	1		T13	16		T17	1
len_601_800	12878	1			T5	3		T13	40		T17	3
len_401_600	8420	1			T1	1		T5	1		T13	31
len_201_400	16565	1			T13	14		T15	251		T17	1
len_65_200	74123	1			T1	1		T5	1		T13	11
len_min_for_xof_require_squeeze	1015	1			T15	10		T78	9		T79	1
len_keccak_block_sizes[72]	755	1			T15	5		T78	9		T128	5
len_keccak_block_sizes[104]	747	1			T15	5		T78	9		T79	2
len_keccak_block_sizes[136]	759	1			T15	5		T78	9		T79	2
len_keccak_block_sizes[144]	285	1			T15	5		T79	1		T128	5
len_keccak_block_sizes[168]	284	1			T15	5		T128	5		T30	1
len_datapath_width	14181	1			T9	3		T5	1		T13	1
len_2_63	215359	1			T1	1		T3	310		T9	6
len_1	50	1			T60	1		T204	1		T205	3