Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1			T133	7		T134	4		T135	7
all_values[1]	284	1			T133	7		T134	4		T135	7
all_values[2]	284	1			T133	7		T134	4		T135	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

518

1

T133

9

T134

7

T135

6

auto[1]

334

1

T133

12

T134

5

T135

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324

1

T133

9

T134

7

T135

12

auto[1]

528

1

T133

12

T134

5

T135

9

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

497

1

T133

13

T134

9

T135

14

auto[1]

355

1

T133

8

T134

3

T135

7

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

58

1

T133

1

T135

1

T182

1

all_values[0]

auto[0]

auto[0]

auto[1]

42

1

T133

2

T183

2

T184

1

all_values[0]

auto[0]

auto[1]

auto[0]

43

1

T133

1

T135

4

T182

1

all_values[0]

auto[0]

auto[1]

auto[1]

21

1

T134

2

T135

1

T183

1

all_values[0]

auto[1]

auto[0]

auto[1]

70

1

T133

1

T134

2

T183

4

all_values[0]

auto[1]

auto[1]

auto[1]

50

1

T133

2

T135

1

T185

1

all_values[1]

auto[0]

auto[0]

auto[0]

82

1

T133

2

T134

1

T135

2

all_values[1]

auto[0]

auto[0]

auto[1]

34

1

T184

1

T186

2

T187

1

all_values[1]

auto[0]

auto[1]

auto[0]

38

1

T133

2

T134

2

T135

1

all_values[1]

auto[0]

auto[1]

auto[1]

18

1

T133

1

T135

1

T183

1

all_values[1]

auto[1]

auto[0]

auto[1]

61

1

T134

1

T135

1

T183

1

all_values[1]

auto[1]

auto[1]

auto[1]

51

1

T133

2

T135

2

T183

1

all_values[2]

auto[0]

auto[0]

auto[0]

57

1

T133

2

T134

3

T135

1

all_values[2]

auto[0]

auto[0]

auto[1]

34

1

T183

1

T187

1

T188

2

all_values[2]

auto[0]

auto[1]

auto[0]

46

1

T133

1

T134

1

T135

3

all_values[2]

auto[0]

auto[1]

auto[1]

24

1

T133

1

T183

1

T184

1

all_values[2]

auto[1]

auto[0]

auto[1]

80

1

T133

1

T135

1

T183

2

all_values[2]

auto[1]

auto[1]

auto[1]

43

1

T133

2

T135

2

T183

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal