Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101005876	1			T1	159750		T2	109868		T3	29266
all_values[1]	101005876	1			T1	159750		T2	109868		T3	29266
all_values[2]	101005876	1			T1	159750		T2	109868		T3	29266

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

639642

1

T1

14

T2

18

T3

460

auto[1]

302377986

1

T1

479236

T2

329586

T3

87338

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301470897

1

T1

477810

T2

328470

T3

86901

auto[1]

1546731

1

T1

1440

T2

1134

T3

897

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	207279	1			T1	1		T2	1		T3	146
all_values[0]	auto[0]	auto[1]	2126	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[0]	100283020	1			T1	159269		T2	109489		T3	28821
all_values[0]	auto[1]	auto[1]	513451	1			T1	478		T2	376		T3	297
all_values[1]	auto[0]	auto[0]	235058	1			T1	6		T13	15		T15	5
all_values[1]	auto[0]	auto[1]	1756	1			T1	5		T13	9		T15	2
all_values[1]	auto[1]	auto[0]	100255241	1			T1	159264		T2	109490		T3	28967
all_values[1]	auto[1]	auto[1]	513821	1			T1	475		T2	378		T3	299
all_values[2]	auto[0]	auto[0]	191694	1			T2	8		T3	309		T15	7
all_values[2]	auto[0]	auto[1]	1729	1			T2	7		T3	3		T15	4
all_values[2]	auto[1]	auto[0]	100298605	1			T1	159270		T2	109482		T3	28658
all_values[2]	auto[1]	auto[1]	513848	1			T1	480		T2	371		T3	296