Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
359724 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
398 |
auto[1] |
342898 |
1 |
|
|
T1 |
618 |
|
T2 |
490 |
|
T13 |
490 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
176796 |
1 |
|
|
T1 |
140 |
|
T2 |
120 |
|
T3 |
123 |
lower_val |
173518 |
1 |
|
|
T1 |
154 |
|
T2 |
123 |
|
T3 |
80 |
zero_val |
1888 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
350776 |
1 |
|
|
T1 |
308 |
|
T2 |
258 |
|
T3 |
204 |
lower_val |
351838 |
1 |
|
|
T1 |
312 |
|
T2 |
234 |
|
T3 |
194 |
zero_val |
8 |
1 |
|
|
T16 |
2 |
|
T147 |
2 |
|
T148 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45179 |
1 |
|
|
T3 |
62 |
|
T13 |
1 |
|
T14 |
11 |
higher_val |
higher_val |
auto[1] |
42868 |
1 |
|
|
T1 |
72 |
|
T2 |
61 |
|
T13 |
55 |
higher_val |
lower_val |
auto[0] |
45361 |
1 |
|
|
T3 |
61 |
|
T14 |
5 |
|
T15 |
5 |
higher_val |
lower_val |
auto[1] |
43386 |
1 |
|
|
T1 |
68 |
|
T2 |
59 |
|
T13 |
64 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T147 |
1 |
|
T149 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
44151 |
1 |
|
|
T3 |
45 |
|
T14 |
25 |
|
T15 |
8 |
lower_val |
higher_val |
auto[1] |
42615 |
1 |
|
|
T1 |
56 |
|
T2 |
53 |
|
T13 |
54 |
lower_val |
lower_val |
auto[0] |
44320 |
1 |
|
|
T1 |
1 |
|
T3 |
35 |
|
T14 |
19 |
lower_val |
lower_val |
auto[1] |
42429 |
1 |
|
|
T1 |
97 |
|
T2 |
70 |
|
T13 |
85 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T147 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T16 |
1 |
|
T148 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
706 |
1 |
|
|
T3 |
1 |
|
T13 |
1 |
|
T17 |
1 |
zero_val |
higher_val |
auto[1] |
257 |
1 |
|
|
T1 |
1 |
|
T13 |
1 |
|
T15 |
1 |
zero_val |
lower_val |
auto[0] |
677 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
248 |
1 |
|
|
T1 |
1 |
|
T13 |
1 |
|
T16 |
5 |