Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101005876	1			T1	159750		T2	109868		T3	29266
all_pins[1]	101005876	1			T1	159750		T2	109868		T3	29266
all_pins[2]	101005876	1			T1	159750		T2	109868		T3	29266

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	245353189	1			T1	351937		T2	245286		T3	74936
values[0x1]	57664439	1			T1	127313		T2	84318		T3	12862
transitions[0x0=>0x1]	57212632	1			T1	126896		T2	83986		T3	12607
transitions[0x1=>0x0]	57212662	1			T1	126896		T2	83986		T3	12607

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100492425	1			T1	159272		T2	109492		T3	28969
all_pins[0]	values[0x1]	513451	1			T1	478		T2	376		T3	297
all_pins[0]	transitions[0x0=>0x1]	220208	1			T1	61		T2	44		T3	42
all_pins[0]	transitions[0x1=>0x0]	56538062	1			T1	126418		T2	83610		T3	12310
all_pins[1]	values[0x0]	44174571	1			T1	32915		T2	25926		T3	16701
all_pins[1]	values[0x1]	56831305	1			T1	126835		T2	83942		T3	12565
all_pins[1]	transitions[0x0=>0x1]	56674697	1			T1	126835		T2	83942		T3	12565
all_pins[1]	transitions[0x1=>0x0]	163075	1			T32	1678		T27	1111		T33	1499
all_pins[2]	values[0x0]	100686193	1			T1	159750		T2	109868		T3	29266
all_pins[2]	values[0x1]	319683	1			T32	1682		T27	2498		T33	1500
all_pins[2]	transitions[0x0=>0x1]	317727	1			T32	1682		T27	2478		T33	1500
all_pins[2]	transitions[0x1=>0x0]	511525	1			T1	478		T2	376		T3	297