Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	698	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5839	1			T3	19		T14	4		T15	19
len_601_800	13311	1			T3	75		T14	14		T15	48
len_401_600	8694	1			T3	55		T14	12		T15	31
len_201_400	16761	1			T3	30		T14	9		T15	9
len_65_200	74567	1			T3	10		T14	4		T15	38
len_min_for_xof_require_squeeze	1003	1			T3	1		T16	9		T18	1
len_keccak_block_sizes[72]	767	1			T16	9		T18	1		T77	1
len_keccak_block_sizes[104]	758	1			T16	9		T176	5		T54	9
len_keccak_block_sizes[136]	766	1			T15	2		T16	9		T18	2
len_keccak_block_sizes[144]	289	1			T15	2		T176	5		T177	5
len_keccak_block_sizes[168]	293	1			T176	5		T177	5		T178	5
len_datapath_width	14238	1			T2	246		T13	246		T14	1
len_2_63	216103	1			T1	310		T3	8		T14	21
len_1	59	1			T18	2		T77	1		T28	2