Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287	1			T111	4		T112	7		T113	7
all_values[1]	287	1			T111	4		T112	7		T113	7
all_values[2]	287	1			T111	4		T112	7		T113	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

481

1

T111

10

T112

16

T113

8

auto[1]

380

1

T111

2

T112

5

T113

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

343

1

T111

2

T112

2

T113

4

auto[1]

518

1

T111

10

T112

19

T113

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

503

1

T111

5

T112

7

T113

10

auto[1]

358

1

T111

7

T112

14

T113

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

67

1

T112

1

T113

1

T156

1

all_values[0]

auto[0]

auto[0]

auto[1]

30

1

T111

1

T112

1

T157

1

all_values[0]

auto[0]

auto[1]

auto[0]

48

1

T111

1

T113

2

T157

1

all_values[0]

auto[0]

auto[1]

auto[1]

25

1

T112

1

T113

1

T158

1

all_values[0]

auto[1]

auto[0]

auto[1]

72

1

T111

2

T112

4

T113

2

all_values[0]

auto[1]

auto[1]

auto[1]

45

1

T113

1

T156

1

T158

1

all_values[1]

auto[0]

auto[0]

auto[0]

63

1

T157

1

T156

1

T159

2

all_values[1]

auto[0]

auto[0]

auto[1]

26

1

T111

1

T112

2

T156

1

all_values[1]

auto[0]

auto[1]

auto[0]

61

1

T111

1

T157

2

T159

2

all_values[1]

auto[0]

auto[1]

auto[1]

25

1

T113

2

T158

3

T160

1

all_values[1]

auto[1]

auto[0]

auto[1]

66

1

T111

2

T112

4

T113

2

all_values[1]

auto[1]

auto[1]

auto[1]

46

1

T112

1

T113

3

T158

1

all_values[2]

auto[0]

auto[0]

auto[0]

58

1

T112

1

T156

1

T158

3

all_values[2]

auto[0]

auto[0]

auto[1]

29

1

T111

1

T113

2

T159

1

all_values[2]

auto[0]

auto[1]

auto[0]

46

1

T113

1

T157

1

T156

3

all_values[2]

auto[0]

auto[1]

auto[1]

25

1

T112

1

T113

1

T157

1

all_values[2]

auto[1]

auto[0]

auto[1]

70

1

T111

3

T112

3

T113

1

all_values[2]

auto[1]

auto[1]

auto[1]

59

1

T112

2

T113

2

T157

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal