Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100213870	1			T1	17257		T2	43637		T3	15
all_values[1]	100213870	1			T1	17257		T2	43637		T3	15
all_values[2]	100213870	1			T1	17257		T2	43637		T3	15

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

524259

1

T1

99

T2

1396

T13

17006

auto[1]

300117351

1

T1

51672

T2

129515

T3

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299103792

1

T1

51171

T2

130776

T3

45

auto[1]

1537818

1

T1

600

T2

135

T9

96

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	169183	1			T1	48		T2	1394		T13	7850
all_values[0]	auto[0]	auto[1]	2179	1			T1	2		T2	2		T13	8
all_values[0]	auto[1]	auto[0]	99532081	1			T1	17009		T2	42198		T3	15
all_values[0]	auto[1]	auto[1]	510427	1			T1	198		T2	43		T9	32
all_values[1]	auto[0]	auto[0]	201419	1			T13	9139		T15	135		T18	1
all_values[1]	auto[0]	auto[1]	1573	1			T13	9		T15	2		T35	2
all_values[1]	auto[1]	auto[0]	99499845	1			T1	17057		T2	43592		T3	15
all_values[1]	auto[1]	auto[1]	511033	1			T1	200		T2	45		T9	32
all_values[2]	auto[0]	auto[0]	148414	1			T1	47		T15	318		T16	4
all_values[2]	auto[0]	auto[1]	1491	1			T1	2		T15	4		T16	2
all_values[2]	auto[1]	auto[0]	99552850	1			T1	17010		T2	43592		T3	15
all_values[2]	auto[1]	auto[1]	511115	1			T1	198		T2	45		T9	32