Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
311896 |
1 |
|
|
T1 |
378 |
|
T2 |
56 |
|
T3 |
2 |
auto[1] |
385508 |
1 |
|
|
T14 |
130 |
|
T15 |
322 |
|
T16 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174181 |
1 |
|
|
T1 |
87 |
|
T2 |
20 |
|
T9 |
10 |
lower_val |
172280 |
1 |
|
|
T1 |
100 |
|
T2 |
10 |
|
T9 |
6 |
zero_val |
1969 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
348940 |
1 |
|
|
T1 |
200 |
|
T2 |
28 |
|
T9 |
26 |
lower_val |
348450 |
1 |
|
|
T1 |
178 |
|
T2 |
28 |
|
T3 |
2 |
zero_val |
14 |
1 |
|
|
T156 |
2 |
|
T157 |
2 |
|
T158 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
[lower_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
38700 |
1 |
|
|
T1 |
44 |
|
T2 |
12 |
|
T9 |
6 |
higher_val |
higher_val |
auto[1] |
48353 |
1 |
|
|
T14 |
15 |
|
T15 |
40 |
|
T16 |
1 |
higher_val |
lower_val |
auto[0] |
39013 |
1 |
|
|
T1 |
43 |
|
T2 |
8 |
|
T9 |
4 |
higher_val |
lower_val |
auto[1] |
48111 |
1 |
|
|
T14 |
15 |
|
T15 |
33 |
|
T16 |
7 |
higher_val |
zero_val |
auto[0] |
4 |
1 |
|
|
T158 |
1 |
|
T159 |
1 |
|
T160 |
1 |
lower_val |
higher_val |
auto[0] |
38523 |
1 |
|
|
T1 |
54 |
|
T2 |
4 |
|
T9 |
3 |
lower_val |
higher_val |
auto[1] |
47705 |
1 |
|
|
T14 |
13 |
|
T15 |
39 |
|
T16 |
1 |
lower_val |
lower_val |
auto[0] |
38517 |
1 |
|
|
T1 |
46 |
|
T2 |
6 |
|
T9 |
3 |
lower_val |
lower_val |
auto[1] |
47533 |
1 |
|
|
T14 |
11 |
|
T15 |
39 |
|
T16 |
2 |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T156 |
1 |
|
T157 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
705 |
1 |
|
|
T1 |
1 |
|
T16 |
1 |
|
T4 |
1 |
zero_val |
higher_val |
auto[1] |
275 |
1 |
|
|
T161 |
4 |
|
T140 |
1 |
|
T162 |
3 |
zero_val |
lower_val |
auto[0] |
722 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T9 |
1 |
zero_val |
lower_val |
auto[1] |
267 |
1 |
|
|
T161 |
2 |
|
T140 |
1 |
|
T162 |
5 |