Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100213870	1			T1	17257		T2	43637		T3	15
all_pins[1]	100213870	1			T1	17257		T2	43637		T3	15
all_pins[2]	100213870	1			T1	17257		T2	43637		T3	15

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299840628	1			T1	51573		T2	130868		T3	45
values[0x1]	800982	1			T1	198		T2	43		T9	32
transitions[0x0=>0x1]	799144	1			T1	198		T2	43		T9	32
transitions[0x1=>0x0]	799167	1			T1	198		T2	43		T9	32

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99703443	1			T1	17059		T2	43594		T3	15
all_pins[0]	values[0x1]	510427	1			T1	198		T2	43		T9	32
all_pins[0]	transitions[0x0=>0x1]	510407	1			T1	198		T2	43		T9	32
all_pins[0]	transitions[0x1=>0x0]	66	1			T19	8		T37	3		T39	4
all_pins[1]	values[0x0]	100213784	1			T1	17257		T2	43637		T3	15
all_pins[1]	values[0x1]	86	1			T19	8		T37	3		T39	4
all_pins[1]	transitions[0x0=>0x1]	72	1			T19	8		T37	3		T39	4
all_pins[1]	transitions[0x1=>0x0]	290455	1			T14	195		T17	4		T26	4463
all_pins[2]	values[0x0]	99923401	1			T1	17257		T2	43637		T3	15
all_pins[2]	values[0x1]	290469	1			T14	195		T17	4		T26	4463
all_pins[2]	transitions[0x0=>0x1]	288665	1			T14	194		T17	4		T26	4432
all_pins[2]	transitions[0x1=>0x0]	508646	1			T1	198		T2	43		T9	32