Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	102546157	1			T1	11996		T2	20843		T3	1350
all_values[1]	102546157	1			T1	11996		T2	20843		T3	1350
all_values[2]	102546157	1			T1	11996		T2	20843		T3	1350

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

541688

1

T2

396

T3

66

T12

53

auto[1]

307096783

1

T1

35988

T2

62133

T3

3984

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

306102399

1

T1

35628

T2

61935

T3

3666

auto[1]

1536072

1

T1

360

T2

594

T3

384

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	180497	1			T2	392		T12	15		T13	7
all_values[0]	auto[0]	auto[1]	2108	1			T2	4		T12	14		T13	2
all_values[0]	auto[1]	auto[0]	101853636	1			T1	11876		T2	20253		T3	1222
all_values[0]	auto[1]	auto[1]	509916	1			T1	120		T2	194		T3	128
all_values[1]	auto[0]	auto[0]	180677	1			T3	52		T12	12		T13	66
all_values[1]	auto[0]	auto[1]	1585	1			T3	4		T12	12		T13	4
all_values[1]	auto[1]	auto[0]	101853456	1			T1	11876		T2	20645		T3	1170
all_values[1]	auto[1]	auto[1]	510439	1			T1	120		T2	198		T3	124
all_values[2]	auto[0]	auto[0]	175285	1			T3	9		T14	14		T15	19
all_values[2]	auto[0]	auto[1]	1536	1			T3	1		T14	4		T15	2
all_values[2]	auto[1]	auto[0]	101858848	1			T1	11876		T2	20645		T3	1213
all_values[2]	auto[1]	auto[1]	510488	1			T1	120		T2	198		T3	127