Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
378636 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
318116 |
1 |
|
|
T1 |
284 |
|
T2 |
282 |
|
T3 |
166 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174335 |
1 |
|
|
T1 |
62 |
|
T2 |
80 |
|
T3 |
49 |
lower_val |
173155 |
1 |
|
|
T1 |
82 |
|
T2 |
67 |
|
T3 |
32 |
zero_val |
1858 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
349696 |
1 |
|
|
T1 |
158 |
|
T2 |
154 |
|
T3 |
88 |
lower_val |
347032 |
1 |
|
|
T1 |
128 |
|
T2 |
130 |
|
T3 |
80 |
zero_val |
24 |
1 |
|
|
T161 |
2 |
|
T162 |
2 |
|
T163 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
47214 |
1 |
|
|
T3 |
1 |
|
T13 |
2 |
|
T14 |
1 |
higher_val |
higher_val |
auto[1] |
40229 |
1 |
|
|
T1 |
33 |
|
T2 |
42 |
|
T3 |
20 |
higher_val |
lower_val |
auto[0] |
47139 |
1 |
|
|
T17 |
4 |
|
T79 |
595 |
|
T77 |
1 |
higher_val |
lower_val |
auto[1] |
39748 |
1 |
|
|
T1 |
29 |
|
T2 |
38 |
|
T3 |
28 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T162 |
1 |
|
T164 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T163 |
1 |
|
T165 |
2 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
47053 |
1 |
|
|
T13 |
5 |
|
T17 |
7 |
|
T18 |
1 |
lower_val |
higher_val |
auto[1] |
39932 |
1 |
|
|
T1 |
49 |
|
T2 |
38 |
|
T3 |
16 |
lower_val |
lower_val |
auto[0] |
46886 |
1 |
|
|
T13 |
2 |
|
T17 |
3 |
|
T79 |
612 |
lower_val |
lower_val |
auto[1] |
39274 |
1 |
|
|
T1 |
33 |
|
T2 |
29 |
|
T3 |
16 |
lower_val |
zero_val |
auto[0] |
9 |
1 |
|
|
T162 |
1 |
|
T164 |
1 |
|
T166 |
2 |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T167 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
717 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
higher_val |
auto[1] |
220 |
1 |
|
|
T89 |
1 |
|
T24 |
2 |
|
T168 |
2 |
zero_val |
lower_val |
auto[0] |
714 |
1 |
|
|
T13 |
1 |
|
T79 |
1 |
|
T77 |
1 |
zero_val |
lower_val |
auto[1] |
207 |
1 |
|
|
T17 |
2 |
|
T89 |
1 |
|
T24 |
1 |