Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10352	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9348	1			T3	13		T12	17		T15	20
len_5001_7500	14945	1			T3	48		T12	17		T15	30
len_2501_5000	9381	1			T3	8		T12	17		T15	10
len_1025_2500	5466	1			T3	8		T12	10		T15	8
len_769_1024	6434	1			T1	15		T2	30		T3	2
len_513_768	6637	1			T1	24		T2	30		T12	2
len_257_512	21137	1			T1	20		T2	44		T12	2
len_0_256	257643	1			T1	22		T2	30		T3	5
len_keccak_block_sizes[72]	715	1			T12	2		T79	3		T77	2
len_keccak_block_sizes[104]	626	1			T2	1		T12	2		T79	3
len_keccak_block_sizes[136]	519	1			T12	2		T79	3		T77	2
len_keccak_block_sizes[144]	420	1			T12	2		T79	3		T86	2
len_keccak_block_sizes[168]	328	1			T79	3		T87	3		T182	3
len_1	746	1			T12	2		T79	3		T77	2
len_0	1179	1			T3	2		T12	2		T14	1