Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	102546157	1			T1	11996		T2	20843		T3	1350
all_pins[1]	102546157	1			T1	11996		T2	20843		T3	1350
all_pins[2]	102546157	1			T1	11996		T2	20843		T3	1350

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	306837348	1			T1	35868		T2	61330		T3	3922
values[0x1]	801123	1			T1	120		T2	1199		T3	128
transitions[0x0=>0x1]	799359	1			T1	120		T2	1199		T3	128
transitions[0x1=>0x0]	799378	1			T1	120		T2	1199		T3	128

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	102036241	1			T1	11876		T2	20649		T3	1222
all_pins[0]	values[0x1]	509916	1			T1	120		T2	194		T3	128
all_pins[0]	transitions[0x0=>0x1]	509900	1			T1	120		T2	194		T3	128
all_pins[0]	transitions[0x1=>0x0]	79	1			T37	3		T38	3		T48	4
all_pins[1]	values[0x0]	102546062	1			T1	11996		T2	20843		T3	1350
all_pins[1]	values[0x1]	95	1			T37	3		T38	3		T48	4
all_pins[1]	transitions[0x0=>0x1]	78	1			T37	3		T38	3		T48	4
all_pins[1]	transitions[0x1=>0x0]	291095	1			T2	1005		T17	2232		T34	129
all_pins[2]	values[0x0]	102255045	1			T1	11996		T2	19838		T3	1350
all_pins[2]	values[0x1]	291112	1			T2	1005		T17	2232		T34	129
all_pins[2]	transitions[0x0=>0x1]	289381	1			T2	1005		T17	2218		T34	129
all_pins[2]	transitions[0x1=>0x0]	508204	1			T1	120		T2	194		T3	128