Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10941177 |
1 |
|
|
T1 |
15753 |
|
T2 |
22175 |
|
T3 |
14068 |
auto[1] |
26033073 |
1 |
|
|
T1 |
24096 |
|
T2 |
33674 |
|
T3 |
20048 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
36854361 |
1 |
|
|
T1 |
39790 |
|
T2 |
55750 |
|
T3 |
34052 |
triple_byte_access |
39854 |
1 |
|
|
T1 |
24 |
|
T2 |
30 |
|
T3 |
26 |
halfword_access |
40249 |
1 |
|
|
T1 |
12 |
|
T2 |
38 |
|
T3 |
20 |
byte_access |
39786 |
1 |
|
|
T1 |
23 |
|
T2 |
31 |
|
T3 |
18 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10821288 |
1 |
|
|
T1 |
15694 |
|
T2 |
22076 |
|
T3 |
14004 |
auto[0] |
triple_byte_access |
39854 |
1 |
|
|
T1 |
24 |
|
T2 |
30 |
|
T3 |
26 |
auto[0] |
halfword_access |
40249 |
1 |
|
|
T1 |
12 |
|
T2 |
38 |
|
T3 |
20 |
auto[0] |
byte_access |
39786 |
1 |
|
|
T1 |
23 |
|
T2 |
31 |
|
T3 |
18 |
auto[1] |
word_access |
26033073 |
1 |
|
|
T1 |
24096 |
|
T2 |
33674 |
|
T3 |
20048 |