Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99903511	1			T1	23424		T2	360		T3	565272
all_values[1]	99903511	1			T1	23424		T2	360		T3	565272
all_values[2]	99903511	1			T1	23424		T2	360		T3	565272

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

511356

1

T1

870

T2

162

T3

14

auto[1]

299199177

1

T1

69402

T2

918

T3

169580

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298182951

1

T1

69585

T2

1074

T3

168530

auto[1]

1527582

1

T1

687

T2

6

T3

10509

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	183839	1			T16	9		T17	1		T18	1921
all_values[0]	auto[0]	auto[1]	2168	1			T16	2		T17	2		T18	8
all_values[0]	auto[1]	auto[0]	99210478	1			T1	23195		T2	358		T3	561769
all_values[0]	auto[1]	auto[1]	507026	1			T1	229		T2	2		T3	3503
all_values[1]	auto[0]	auto[0]	170667	1			T1	149		T2	80		T3	4
all_values[1]	auto[0]	auto[1]	1783	1			T1	1		T2	1		T3	3
all_values[1]	auto[1]	auto[0]	99223650	1			T1	23046		T2	278		T3	561765
all_values[1]	auto[1]	auto[1]	507411	1			T1	228		T2	1		T3	3500
all_values[2]	auto[0]	auto[0]	151221	1			T1	714		T2	80		T3	4
all_values[2]	auto[0]	auto[1]	1678	1			T1	6		T2	1		T3	3
all_values[2]	auto[1]	auto[0]	99243096	1			T1	22481		T2	278		T3	561765
all_values[2]	auto[1]	auto[1]	507516	1			T1	223		T2	1		T3	3500