Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99903511	1			T1	23424		T2	360		T3	565272
all_pins[1]	99903511	1			T1	23424		T2	360		T3	565272
all_pins[2]	99903511	1			T1	23424		T2	360		T3	565272

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298922727	1			T1	70043		T2	1078		T3	169231
values[0x1]	787806	1			T1	229		T2	2		T3	3503
transitions[0x0=>0x1]	786107	1			T1	229		T2	2		T3	3503
transitions[0x1=>0x0]	786135	1			T1	229		T2	2		T3	3503

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99396485	1			T1	23195		T2	358		T3	561769
all_pins[0]	values[0x1]	507026	1			T1	229		T2	2		T3	3503
all_pins[0]	transitions[0x0=>0x1]	507015	1			T1	229		T2	2		T3	3503
all_pins[0]	transitions[0x1=>0x0]	61	1			T44	3		T173	9		T174	3
all_pins[1]	values[0x0]	99903439	1			T1	23424		T2	360		T3	565272
all_pins[1]	values[0x1]	72	1			T44	3		T173	9		T174	3
all_pins[1]	transitions[0x0=>0x1]	66	1			T44	3		T173	9		T174	3
all_pins[1]	transitions[0x1=>0x0]	280702	1			T18	2851		T29	105		T24	2569
all_pins[2]	values[0x0]	99622803	1			T1	23424		T2	360		T3	565272
all_pins[2]	values[0x1]	280708	1			T18	2851		T29	105		T24	2569
all_pins[2]	transitions[0x0=>0x1]	279026	1			T18	2836		T29	105		T24	2556
all_pins[2]	transitions[0x1=>0x0]	505372	1			T1	229		T2	2		T3	3503