Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101336300	1			T1	20505		T3	225570		T4	180997
all_values[1]	101336300	1			T1	20505		T3	225570		T4	180997
all_values[2]	101336300	1			T1	20505		T3	225570		T4	180997

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

578431

1

T1

463

T3

10

T4

6729

auto[1]

303430469

1

T1

61052

T3

676700

T4

536262

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

302475147

1

T1

60942

T3

674967

T4

542484

auto[1]

1533753

1

T1

573

T3

1743

T4

507

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	214156	1			T3	1		T4	2241		T13	1
all_values[0]	auto[0]	auto[1]	2183	1			T3	2		T4	2		T15	2
all_values[0]	auto[1]	auto[0]	100610893	1			T1	20314		T3	224988		T4	178587
all_values[0]	auto[1]	auto[1]	509068	1			T1	191		T3	579		T4	167
all_values[1]	auto[0]	auto[0]	176662	1			T4	2241		T13	1		T16	203
all_values[1]	auto[0]	auto[1]	1642	1			T4	2		T16	2		T17	7
all_values[1]	auto[1]	auto[0]	100648387	1			T1	20314		T3	224989		T4	178587
all_values[1]	auto[1]	auto[1]	509609	1			T1	191		T3	581		T4	167
all_values[2]	auto[0]	auto[0]	182167	1			T1	459		T3	4		T4	2241
all_values[2]	auto[0]	auto[1]	1621	1			T1	4		T3	3		T4	2
all_values[2]	auto[1]	auto[0]	100642882	1			T1	19855		T3	224985		T4	178587
all_values[2]	auto[1]	auto[1]	509630	1			T1	187		T3	578		T4	167