Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
341288 |
1 |
|
|
T1 |
334 |
|
T3 |
780 |
|
T4 |
2 |
auto[1] |
354650 |
1 |
|
|
T4 |
224 |
|
T14 |
344 |
|
T15 |
14 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173631 |
1 |
|
|
T1 |
88 |
|
T3 |
179 |
|
T4 |
56 |
lower_val |
172619 |
1 |
|
|
T1 |
100 |
|
T3 |
226 |
|
T4 |
54 |
zero_val |
1923 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
347460 |
1 |
|
|
T1 |
174 |
|
T3 |
380 |
|
T4 |
118 |
lower_val |
348464 |
1 |
|
|
T1 |
160 |
|
T3 |
400 |
|
T4 |
108 |
zero_val |
14 |
1 |
|
|
T161 |
2 |
|
T162 |
2 |
|
T163 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42397 |
1 |
|
|
T1 |
45 |
|
T3 |
90 |
|
T13 |
7 |
higher_val |
higher_val |
auto[1] |
44359 |
1 |
|
|
T4 |
29 |
|
T14 |
56 |
|
T15 |
2 |
higher_val |
lower_val |
auto[0] |
42641 |
1 |
|
|
T1 |
43 |
|
T3 |
89 |
|
T13 |
19 |
higher_val |
lower_val |
auto[1] |
44232 |
1 |
|
|
T4 |
27 |
|
T14 |
44 |
|
T15 |
2 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T164 |
1 |
|
- |
- |
|
- |
- |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T165 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
42285 |
1 |
|
|
T1 |
56 |
|
T3 |
110 |
|
T13 |
13 |
lower_val |
higher_val |
auto[1] |
44016 |
1 |
|
|
T4 |
28 |
|
T14 |
32 |
|
T15 |
1 |
lower_val |
lower_val |
auto[0] |
42117 |
1 |
|
|
T1 |
44 |
|
T3 |
116 |
|
T13 |
9 |
lower_val |
lower_val |
auto[1] |
44196 |
1 |
|
|
T4 |
26 |
|
T14 |
36 |
|
T15 |
1 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T161 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
4 |
1 |
|
|
T162 |
1 |
|
T163 |
1 |
|
T166 |
1 |
zero_val |
higher_val |
auto[0] |
758 |
1 |
|
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
1 |
zero_val |
higher_val |
auto[1] |
221 |
1 |
|
|
T167 |
6 |
|
T168 |
1 |
|
T169 |
2 |
zero_val |
lower_val |
auto[0] |
678 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
266 |
1 |
|
|
T18 |
2 |
|
T168 |
1 |
|
T170 |
1 |