Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101336300	1			T1	20505		T3	225570		T4	180997
all_pins[1]	101336300	1			T1	20505		T3	225570		T4	180997
all_pins[2]	101336300	1			T1	20505		T3	225570		T4	180997

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	303165137	1			T1	61324		T3	676131		T4	542824
values[0x1]	843763	1			T1	191		T3	579		T4	167
transitions[0x0=>0x1]	841730	1			T1	191		T3	579		T4	167
transitions[0x1=>0x0]	841755	1			T1	191		T3	579		T4	167

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100827232	1			T1	20314		T3	224991		T4	180830
all_pins[0]	values[0x1]	509068	1			T1	191		T3	579		T4	167
all_pins[0]	transitions[0x0=>0x1]	509045	1			T1	191		T3	579		T4	167
all_pins[0]	transitions[0x1=>0x0]	58	1			T175	2		T114	3		T176	2
all_pins[1]	values[0x0]	101336219	1			T1	20505		T3	225570		T4	180997
all_pins[1]	values[0x1]	81	1			T175	2		T114	3		T176	2
all_pins[1]	transitions[0x0=>0x1]	66	1			T175	2		T114	3		T176	2
all_pins[1]	transitions[0x1=>0x0]	334599	1			T16	615		T31	1929		T45	425
all_pins[2]	values[0x0]	101001686	1			T1	20505		T3	225570		T4	180997
all_pins[2]	values[0x1]	334614	1			T16	615		T31	1929		T45	425
all_pins[2]	transitions[0x0=>0x1]	332619	1			T16	615		T31	1929		T45	425
all_pins[2]	transitions[0x1=>0x0]	507098	1			T1	191		T3	579		T4	167