Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99650540	1			T1	20385		T4	22637		T5	7736
all_values[1]	99650540	1			T1	20385		T4	22637		T5	7736
all_values[2]	99650540	1			T1	20385		T4	22637		T5	7736

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

513160

1

T1

207

T4

1110

T5

809

auto[1]

298438460

1

T1

60948

T4

66801

T5

22399

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297422595

1

T1

60546

T4

67029

T5

22965

auto[1]

1529025

1

T1

609

T4

882

T5

243

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	168225	1			T1	204		T4	331		T5	1
all_values[0]	auto[0]	auto[1]	2216	1			T1	2		T4	8		T16	4
all_values[0]	auto[1]	auto[0]	98972640	1			T1	19978		T4	22012		T5	7654
all_values[0]	auto[1]	auto[1]	507459	1			T1	201		T4	286		T5	81
all_values[1]	auto[0]	auto[0]	165773	1			T1	1		T4	635		T5	357
all_values[1]	auto[0]	auto[1]	1552	1			T4	17		T5	4		T17	2
all_values[1]	auto[1]	auto[0]	98975092	1			T1	20181		T4	21708		T5	7298
all_values[1]	auto[1]	auto[1]	508123	1			T1	203		T4	277		T5	77
all_values[2]	auto[0]	auto[0]	173801	1			T4	116		T5	441		T15	2220
all_values[2]	auto[0]	auto[1]	1593	1			T4	3		T5	6		T15	1
all_values[2]	auto[1]	auto[0]	98967064	1			T1	20182		T4	22227		T5	7214
all_values[2]	auto[1]	auto[1]	508082	1			T1	203		T4	291		T5	75