Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
318416 |
1 |
|
|
T1 |
398 |
|
T4 |
212 |
|
T5 |
46 |
auto[1] |
374886 |
1 |
|
|
T4 |
274 |
|
T5 |
102 |
|
T18 |
362 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174187 |
1 |
|
|
T1 |
92 |
|
T4 |
104 |
|
T5 |
39 |
lower_val |
171569 |
1 |
|
|
T1 |
118 |
|
T4 |
132 |
|
T5 |
35 |
zero_val |
1783 |
1 |
|
|
T1 |
1 |
|
T4 |
9 |
|
T5 |
5 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
345784 |
1 |
|
|
T1 |
190 |
|
T4 |
250 |
|
T5 |
76 |
lower_val |
347512 |
1 |
|
|
T1 |
208 |
|
T4 |
236 |
|
T5 |
72 |
zero_val |
6 |
1 |
|
|
T154 |
2 |
|
T155 |
2 |
|
T156 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
[lower_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
39591 |
1 |
|
|
T1 |
47 |
|
T4 |
30 |
|
T5 |
5 |
higher_val |
higher_val |
auto[1] |
47022 |
1 |
|
|
T4 |
24 |
|
T5 |
11 |
|
T18 |
41 |
higher_val |
lower_val |
auto[0] |
40057 |
1 |
|
|
T1 |
45 |
|
T4 |
28 |
|
T5 |
6 |
higher_val |
lower_val |
auto[1] |
47516 |
1 |
|
|
T4 |
22 |
|
T5 |
17 |
|
T18 |
63 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T155 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
39166 |
1 |
|
|
T1 |
61 |
|
T4 |
25 |
|
T5 |
4 |
lower_val |
higher_val |
auto[1] |
46415 |
1 |
|
|
T4 |
35 |
|
T5 |
15 |
|
T18 |
41 |
lower_val |
lower_val |
auto[0] |
39443 |
1 |
|
|
T1 |
57 |
|
T4 |
29 |
|
T5 |
5 |
lower_val |
lower_val |
auto[1] |
46544 |
1 |
|
|
T4 |
43 |
|
T5 |
11 |
|
T18 |
61 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T154 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
674 |
1 |
|
|
T4 |
4 |
|
T5 |
2 |
|
T16 |
1 |
zero_val |
higher_val |
auto[1] |
220 |
1 |
|
|
T4 |
2 |
|
T5 |
1 |
|
T157 |
2 |
zero_val |
lower_val |
auto[0] |
645 |
1 |
|
|
T1 |
1 |
|
T5 |
2 |
|
T15 |
1 |
zero_val |
lower_val |
auto[1] |
244 |
1 |
|
|
T4 |
3 |
|
T157 |
6 |
|
T128 |
1 |