Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99650540	1			T1	20385		T4	22637		T5	7736
all_pins[1]	99650540	1			T1	20385		T4	22637		T5	7736
all_pins[2]	99650540	1			T1	20385		T4	22637		T5	7736

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298122629	1			T1	60954		T4	64934		T5	19910
values[0x1]	828991	1			T1	201		T4	2977		T5	3298
transitions[0x0=>0x1]	827031	1			T1	201		T4	2958		T5	3276
transitions[0x1=>0x0]	827052	1			T1	201		T4	2958		T5	3276

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99143081	1			T1	20184		T4	22351		T5	7655
all_pins[0]	values[0x1]	507459	1			T1	201		T4	286		T5	81
all_pins[0]	transitions[0x0=>0x1]	507449	1			T1	201		T4	286		T5	81
all_pins[0]	transitions[0x1=>0x0]	51	1			T38	8		T166	3		T167	5
all_pins[1]	values[0x0]	99650479	1			T1	20385		T4	22637		T5	7736
all_pins[1]	values[0x1]	61	1			T38	8		T166	3		T167	5
all_pins[1]	transitions[0x0=>0x1]	53	1			T38	8		T166	3		T167	5
all_pins[1]	transitions[0x1=>0x0]	321463	1			T4	2691		T5	3217		T28	482
all_pins[2]	values[0x0]	99329069	1			T1	20385		T4	19946		T5	4519
all_pins[2]	values[0x1]	321471	1			T4	2691		T5	3217		T28	482
all_pins[2]	transitions[0x0=>0x1]	319529	1			T4	2672		T5	3195		T28	482
all_pins[2]	transitions[0x1=>0x0]	505538	1			T1	201		T4	267		T5	59