Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	612	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5468	1			T1	25		T4	26		T5	6
len_601_800	12317	1			T1	49		T4	48		T5	22
len_401_600	8044	1			T1	33		T4	42		T5	9
len_201_400	16443	1			T1	20		T4	16		T5	4
len_65_200	73710	1			T1	3		T4	12		T5	3
len_min_for_xof_require_squeeze	1014	1			T17	10		T18	2		T76	9
len_keccak_block_sizes[72]	750	1			T17	5		T18	1		T76	9
len_keccak_block_sizes[104]	755	1			T17	5		T18	2		T76	9
len_keccak_block_sizes[136]	756	1			T17	5		T18	1		T76	9
len_keccak_block_sizes[144]	282	1			T4	1		T17	5		T157	5
len_keccak_block_sizes[168]	285	1			T5	1		T17	5		T83	1
len_datapath_width	14156	1			T4	13		T5	3		T16	3
len_2_63	214812	1			T1	68		T4	86		T5	26
len_1	44	1			T18	1		T181	1		T135	1