Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10625336 |
1 |
|
|
T1 |
24973 |
|
T4 |
26351 |
|
T5 |
7712 |
auto[1] |
25575492 |
1 |
|
|
T1 |
37052 |
|
T4 |
41210 |
|
T5 |
11846 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
36082222 |
1 |
|
|
T1 |
61925 |
|
T4 |
67447 |
|
T5 |
19522 |
triple_byte_access |
39588 |
1 |
|
|
T1 |
35 |
|
T4 |
43 |
|
T5 |
13 |
halfword_access |
39652 |
1 |
|
|
T1 |
33 |
|
T4 |
35 |
|
T5 |
11 |
byte_access |
39366 |
1 |
|
|
T1 |
32 |
|
T4 |
36 |
|
T5 |
12 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10506730 |
1 |
|
|
T1 |
24873 |
|
T4 |
26237 |
|
T5 |
7676 |
auto[0] |
triple_byte_access |
39588 |
1 |
|
|
T1 |
35 |
|
T4 |
43 |
|
T5 |
13 |
auto[0] |
halfword_access |
39652 |
1 |
|
|
T1 |
33 |
|
T4 |
35 |
|
T5 |
11 |
auto[0] |
byte_access |
39366 |
1 |
|
|
T1 |
32 |
|
T4 |
36 |
|
T5 |
12 |
auto[1] |
word_access |
25575492 |
1 |
|
|
T1 |
37052 |
|
T4 |
41210 |
|
T5 |
11846 |