Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 290 1 T111 4 T112 4 T113 7
all_values[1] 290 1 T111 4 T112 4 T113 7
all_values[2] 290 1 T111 4 T112 4 T113 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 478 1 T111 7 T112 9 T113 13
auto[1] 392 1 T111 5 T112 3 T113 8


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 423 1 T111 4 T112 4 T113 8
auto[1] 447 1 T111 8 T112 8 T113 13


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 522 1 T111 5 T112 7 T113 10
auto[1] 348 1 T111 7 T112 5 T113 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 75 1 T111 1 T113 1 T162 1
all_values[0] auto[0] auto[0] auto[1] 19 1 T112 1 T163 1 T164 1
all_values[0] auto[0] auto[1] auto[0] 43 1 T111 2 T152 1 T165 2
all_values[0] auto[0] auto[1] auto[1] 27 1 T112 1 T113 1 T152 1
all_values[0] auto[1] auto[0] auto[1] 69 1 T111 1 T113 3 T152 1
all_values[0] auto[1] auto[1] auto[1] 57 1 T112 2 T113 2 T152 4
all_values[1] auto[0] auto[0] auto[0] 100 1 T111 1 T112 3 T113 3
all_values[1] auto[0] auto[1] auto[0] 81 1 T113 1 T152 4 T162 3
all_values[1] auto[1] auto[0] auto[1] 60 1 T111 2 T112 1 T113 1
all_values[1] auto[1] auto[1] auto[1] 49 1 T111 1 T113 2 T152 3
all_values[2] auto[0] auto[0] auto[0] 71 1 T112 1 T113 1 T152 1
all_values[2] auto[0] auto[0] auto[1] 28 1 T112 1 T113 1 T165 1
all_values[2] auto[0] auto[1] auto[0] 53 1 T113 2 T152 2 T162 3
all_values[2] auto[0] auto[1] auto[1] 25 1 T111 1 T152 2 T165 1
all_values[2] auto[1] auto[0] auto[1] 56 1 T111 2 T112 2 T113 3
all_values[2] auto[1] auto[1] auto[1] 57 1 T111 1 T152 2 T162 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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