Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	102371992	1			T1	219815		T2	108662		T3	7516
all_values[1]	102371992	1			T1	219815		T2	108662		T3	7516
all_values[2]	102371992	1			T1	219815		T2	108662		T3	7516

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

665830

1

T2

36

T3

1

T13

6

auto[1]

306450146

1

T1

659445

T2

325950

T3

22547

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

305575746

1

T1

657717

T2

324867

T3

22317

auto[1]

1540230

1

T1

1728

T2

1119

T3

231

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	200374	1			T13	1		T14	630		T17	517
all_values[0]	auto[0]	auto[1]	2168	1			T13	2		T14	30		T17	6
all_values[0]	auto[1]	auto[0]	101658208	1			T1	219239		T2	108289		T3	7439
all_values[0]	auto[1]	auto[1]	511242	1			T1	576		T2	373		T3	77
all_values[1]	auto[0]	auto[0]	227093	1			T2	13		T3	1		T13	1
all_values[1]	auto[0]	auto[1]	1634	1			T2	7		T13	2		T14	21
all_values[1]	auto[1]	auto[0]	101631489	1			T1	219239		T2	108276		T3	7438
all_values[1]	auto[1]	auto[1]	511776	1			T1	576		T2	366		T3	77
all_values[2]	auto[0]	auto[0]	232961	1			T2	10		T4	9		T14	692
all_values[2]	auto[0]	auto[1]	1600	1			T2	6		T14	9		T15	3
all_values[2]	auto[1]	auto[0]	101625621	1			T1	219239		T2	108279		T3	7439
all_values[2]	auto[1]	auto[1]	511810	1			T1	576		T2	367		T3	77