Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
350254 |
1 |
|
|
T1 |
780 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
349010 |
1 |
|
|
T2 |
490 |
|
T3 |
168 |
|
T13 |
490 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
175075 |
1 |
|
|
T1 |
193 |
|
T2 |
146 |
|
T3 |
44 |
lower_val |
173386 |
1 |
|
|
T1 |
196 |
|
T2 |
126 |
|
T3 |
32 |
zero_val |
1793 |
1 |
|
|
T1 |
3 |
|
T2 |
5 |
|
T3 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
348812 |
1 |
|
|
T1 |
420 |
|
T2 |
240 |
|
T3 |
100 |
lower_val |
350444 |
1 |
|
|
T1 |
360 |
|
T2 |
252 |
|
T3 |
70 |
zero_val |
8 |
1 |
|
|
T156 |
2 |
|
T157 |
2 |
|
T158 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43642 |
1 |
|
|
T1 |
98 |
|
T2 |
1 |
|
T14 |
58 |
higher_val |
higher_val |
auto[1] |
43638 |
1 |
|
|
T2 |
77 |
|
T3 |
23 |
|
T13 |
52 |
higher_val |
lower_val |
auto[0] |
44161 |
1 |
|
|
T1 |
95 |
|
T14 |
43 |
|
T16 |
90 |
higher_val |
lower_val |
auto[1] |
43633 |
1 |
|
|
T2 |
68 |
|
T3 |
21 |
|
T13 |
76 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T157 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
43290 |
1 |
|
|
T1 |
110 |
|
T4 |
1 |
|
T14 |
59 |
lower_val |
higher_val |
auto[1] |
43250 |
1 |
|
|
T2 |
55 |
|
T3 |
16 |
|
T13 |
73 |
lower_val |
lower_val |
auto[0] |
43532 |
1 |
|
|
T1 |
86 |
|
T14 |
38 |
|
T16 |
116 |
lower_val |
lower_val |
auto[1] |
43310 |
1 |
|
|
T2 |
71 |
|
T3 |
16 |
|
T13 |
58 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T157 |
1 |
|
T159 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T156 |
2 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
677 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
higher_val |
auto[1] |
223 |
1 |
|
|
T2 |
3 |
|
T3 |
2 |
|
T14 |
2 |
zero_val |
lower_val |
auto[0] |
651 |
1 |
|
|
T1 |
1 |
|
T14 |
2 |
|
T16 |
1 |
zero_val |
lower_val |
auto[1] |
242 |
1 |
|
|
T2 |
1 |
|
T14 |
1 |
|
T38 |
2 |