Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	102371992	1			T1	219815		T2	108662		T3	7516
all_pins[1]	102371992	1			T1	219815		T2	108662		T3	7516
all_pins[2]	102371992	1			T1	219815		T2	108662		T3	7516

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	306318324	1			T1	658869		T2	325613		T3	22471
values[0x1]	797652	1			T1	576		T2	373		T3	77
transitions[0x0=>0x1]	795919	1			T1	576		T2	373		T3	77
transitions[0x1=>0x0]	795941	1			T1	576		T2	373		T3	77

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	101860750	1			T1	219239		T2	108289		T3	7439
all_pins[0]	values[0x1]	511242	1			T1	576		T2	373		T3	77
all_pins[0]	transitions[0x0=>0x1]	511228	1			T1	576		T2	373		T3	77
all_pins[0]	transitions[0x1=>0x0]	65	1			T43	3		T172	3		T173	7
all_pins[1]	values[0x0]	102371913	1			T1	219815		T2	108662		T3	7516
all_pins[1]	values[0x1]	79	1			T43	3		T172	3		T173	7
all_pins[1]	transitions[0x0=>0x1]	63	1			T43	3		T172	3		T173	7
all_pins[1]	transitions[0x1=>0x0]	286315	1			T14	3979		T26	5924		T45	244
all_pins[2]	values[0x0]	102085661	1			T1	219815		T2	108662		T3	7516
all_pins[2]	values[0x1]	286331	1			T14	3979		T26	5924		T45	244
all_pins[2]	transitions[0x0=>0x1]	284628	1			T14	3953		T26	5882		T45	244
all_pins[2]	transitions[0x1=>0x0]	509561	1			T1	576		T2	373		T3	77