Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
102371992 |
1 |
|
|
T1 |
219815 |
|
T2 |
108662 |
|
T3 |
7516 |
all_pins[1] |
102371992 |
1 |
|
|
T1 |
219815 |
|
T2 |
108662 |
|
T3 |
7516 |
all_pins[2] |
102371992 |
1 |
|
|
T1 |
219815 |
|
T2 |
108662 |
|
T3 |
7516 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
306318324 |
1 |
|
|
T1 |
658869 |
|
T2 |
325613 |
|
T3 |
22471 |
values[0x1] |
797652 |
1 |
|
|
T1 |
576 |
|
T2 |
373 |
|
T3 |
77 |
transitions[0x0=>0x1] |
795919 |
1 |
|
|
T1 |
576 |
|
T2 |
373 |
|
T3 |
77 |
transitions[0x1=>0x0] |
795941 |
1 |
|
|
T1 |
576 |
|
T2 |
373 |
|
T3 |
77 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
12 |
0 |
12 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
101860750 |
1 |
|
|
T1 |
219239 |
|
T2 |
108289 |
|
T3 |
7439 |
all_pins[0] |
values[0x1] |
511242 |
1 |
|
|
T1 |
576 |
|
T2 |
373 |
|
T3 |
77 |
all_pins[0] |
transitions[0x0=>0x1] |
511228 |
1 |
|
|
T1 |
576 |
|
T2 |
373 |
|
T3 |
77 |
all_pins[0] |
transitions[0x1=>0x0] |
65 |
1 |
|
|
T43 |
3 |
|
T172 |
3 |
|
T173 |
7 |
all_pins[1] |
values[0x0] |
102371913 |
1 |
|
|
T1 |
219815 |
|
T2 |
108662 |
|
T3 |
7516 |
all_pins[1] |
values[0x1] |
79 |
1 |
|
|
T43 |
3 |
|
T172 |
3 |
|
T173 |
7 |
all_pins[1] |
transitions[0x0=>0x1] |
63 |
1 |
|
|
T43 |
3 |
|
T172 |
3 |
|
T173 |
7 |
all_pins[1] |
transitions[0x1=>0x0] |
286315 |
1 |
|
|
T14 |
3979 |
|
T26 |
5924 |
|
T45 |
244 |
all_pins[2] |
values[0x0] |
102085661 |
1 |
|
|
T1 |
219815 |
|
T2 |
108662 |
|
T3 |
7516 |
all_pins[2] |
values[0x1] |
286331 |
1 |
|
|
T14 |
3979 |
|
T26 |
5924 |
|
T45 |
244 |
all_pins[2] |
transitions[0x0=>0x1] |
284628 |
1 |
|
|
T14 |
3953 |
|
T26 |
5882 |
|
T45 |
244 |
all_pins[2] |
transitions[0x1=>0x0] |
509561 |
1 |
|
|
T1 |
576 |
|
T2 |
373 |
|
T3 |
77 |