Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::sideload_cg

Group : kmac_env_pkg::kmac_env_cov::sideload_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::sideload_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::sideload_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
in_app_keymgr	2	0	2	100.00	100	1	1	2
kmac_mode	2	0	2	100.00	100	1	1	2
sideload	2	0	2	100.00	100	1	1	2

Crosses for Group kmac_env_pkg::kmac_env_cov::sideload_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_cross	4	0	4	100.00	100	1	1	0

Summary for Variable in_app_keymgr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for in_app_keymgr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

343606

1

T1

377

T2

236

T3

104

auto[1]

3369

1

T3

13

T14

32

T17

14

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Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

308092

1

T1

377

T2

236

T3

57

auto[1]

38883

1

T3

60

T14

287

T15

129

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Summary for Variable sideload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sideload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

333267

1

T1

377

T2

236

T3

87

auto[1]

13708

1

T3

30

T14

64

T15

179

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Summary for Cross sideload_cross

Samples crossed: sideload kmac_mode in_app_keymgr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	4	0	4	100.00

User Defined Cross Bins for sideload_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sw_kmac_valid_sideload	13708	1			T3	30		T14	64		T15	179
sw_kmac_invalid_sideload	333267	1			T1	377		T2	236		T3	87
app_valid_sideload	13708	1			T3	30		T14	64		T15	179
app_invalid_sideload	333267	1			T1	377		T2	236		T3	87