Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 278 1 T122 7 T123 7 T124 7
all_values[1] 278 1 T122 7 T123 7 T124 7
all_values[2] 278 1 T122 7 T123 7 T124 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 459 1 T122 15 T123 9 T124 14
auto[1] 375 1 T122 6 T123 12 T124 7


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 352 1 T122 10 T123 5 T124 6
auto[1] 482 1 T122 11 T123 16 T124 15


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 472 1 T122 12 T123 10 T124 10
auto[1] 362 1 T122 9 T123 11 T124 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 56 1 T122 2 T123 2 T124 1
all_values[0] auto[0] auto[0] auto[1] 30 1 T124 2 T153 2 T168 1
all_values[0] auto[0] auto[1] auto[0] 53 1 T122 4 T123 1 T169 1
all_values[0] auto[0] auto[1] auto[1] 24 1 T123 1 T170 2 T171 1
all_values[0] auto[1] auto[0] auto[1] 61 1 T122 1 T124 3 T153 1
all_values[0] auto[1] auto[1] auto[1] 54 1 T123 3 T124 1 T153 3
all_values[1] auto[0] auto[0] auto[0] 79 1 T122 3 T123 1 T124 3
all_values[1] auto[0] auto[1] auto[0] 78 1 T123 1 T153 3 T169 2
all_values[1] auto[1] auto[0] auto[1] 74 1 T122 3 T123 2 T124 4
all_values[1] auto[1] auto[1] auto[1] 47 1 T122 1 T123 3 T153 3
all_values[2] auto[0] auto[0] auto[0] 51 1 T122 1 T124 1 T153 1
all_values[2] auto[0] auto[0] auto[1] 31 1 T122 2 T123 3 T153 1
all_values[2] auto[0] auto[1] auto[0] 35 1 T124 1 T153 2 T169 1
all_values[2] auto[0] auto[1] auto[1] 35 1 T123 1 T124 2 T169 1
all_values[2] auto[1] auto[0] auto[1] 77 1 T122 3 T123 1 T153 1
all_values[2] auto[1] auto[1] auto[1] 49 1 T122 1 T123 2 T124 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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