Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101180083	1			T1	174225		T2	1610		T3	83
all_values[1]	101180083	1			T1	174225		T2	1610		T3	83
all_values[2]	101180083	1			T1	174225		T2	1610		T3	83

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

472015

1

T1

4248

T2

9

T3

3

auto[1]

303068234

1

T1

518427

T2

4821

T3

246

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

302005671

1

T1

522096

T2

4377

T3

249

auto[1]

1534578

1

T1

579

T2

453

T13

501

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	148250	1			T1	2122		T2	7		T13	87
all_values[0]	auto[0]	auto[1]	2090	1			T1	2		T2	2		T13	2
all_values[0]	auto[1]	auto[0]	100520307	1			T1	171910		T2	1452		T3	83
all_values[0]	auto[1]	auto[1]	509436	1			T1	191		T2	149		T13	165
all_values[1]	auto[0]	auto[0]	129605	1			T3	2		T13	237		T14	16
all_values[1]	auto[0]	auto[1]	1422	1			T13	3		T14	2		T15	2
all_values[1]	auto[1]	auto[0]	100538952	1			T1	174032		T2	1459		T3	81
all_values[1]	auto[1]	auto[1]	510104	1			T1	193		T2	151		T13	164
all_values[2]	auto[0]	auto[0]	189119	1			T1	2122		T3	1		T13	418
all_values[2]	auto[0]	auto[1]	1529	1			T1	2		T13	6		T16	3
all_values[2]	auto[1]	auto[0]	100479438	1			T1	171910		T2	1459		T3	82
all_values[2]	auto[1]	auto[1]	509997	1			T1	191		T2	151		T13	161