Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
369408 |
1 |
|
|
T1 |
250 |
|
T2 |
196 |
|
T3 |
2 |
auto[1] |
325420 |
1 |
|
|
T3 |
162 |
|
T13 |
214 |
|
T14 |
32 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172761 |
1 |
|
|
T1 |
60 |
|
T2 |
40 |
|
T3 |
34 |
lower_val |
172645 |
1 |
|
|
T1 |
53 |
|
T2 |
48 |
|
T3 |
42 |
zero_val |
1780 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
348378 |
1 |
|
|
T1 |
124 |
|
T2 |
104 |
|
T3 |
104 |
lower_val |
346444 |
1 |
|
|
T1 |
126 |
|
T2 |
92 |
|
T3 |
60 |
zero_val |
6 |
1 |
|
|
T155 |
2 |
|
T156 |
2 |
|
T157 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45961 |
1 |
|
|
T1 |
36 |
|
T2 |
18 |
|
T14 |
1 |
higher_val |
higher_val |
auto[1] |
40460 |
1 |
|
|
T3 |
22 |
|
T13 |
15 |
|
T14 |
8 |
higher_val |
lower_val |
auto[0] |
45884 |
1 |
|
|
T1 |
24 |
|
T2 |
22 |
|
T13 |
1 |
higher_val |
lower_val |
auto[1] |
40453 |
1 |
|
|
T3 |
12 |
|
T13 |
42 |
|
T14 |
5 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T156 |
1 |
|
T157 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T155 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
45666 |
1 |
|
|
T1 |
26 |
|
T2 |
26 |
|
T15 |
71 |
lower_val |
higher_val |
auto[1] |
40764 |
1 |
|
|
T3 |
25 |
|
T13 |
24 |
|
T14 |
4 |
lower_val |
lower_val |
auto[0] |
45908 |
1 |
|
|
T1 |
27 |
|
T2 |
22 |
|
T15 |
65 |
lower_val |
lower_val |
auto[1] |
40305 |
1 |
|
|
T3 |
17 |
|
T13 |
28 |
|
T14 |
3 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T157 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T155 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
667 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T14 |
1 |
zero_val |
higher_val |
auto[1] |
223 |
1 |
|
|
T23 |
2 |
|
T89 |
3 |
|
T158 |
1 |
zero_val |
lower_val |
auto[0] |
676 |
1 |
|
|
T2 |
1 |
|
T13 |
1 |
|
T16 |
1 |
zero_val |
lower_val |
auto[1] |
214 |
1 |
|
|
T23 |
1 |
|
T89 |
1 |
|
T158 |
1 |