Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101180083	1			T1	174225		T2	1610		T3	83
all_pins[1]	101180083	1			T1	174225		T2	1610		T3	83
all_pins[2]	101180083	1			T1	174225		T2	1610		T3	83

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	302707613	1			T1	522484		T2	4681		T3	249
values[0x1]	832636	1			T1	191		T2	149		T13	165
transitions[0x0=>0x1]	830679	1			T1	191		T2	149		T13	165
transitions[0x1=>0x0]	830697	1			T1	191		T2	149		T13	165

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100670647	1			T1	174034		T2	1461		T3	83
all_pins[0]	values[0x1]	509436	1			T1	191		T2	149		T13	165
all_pins[0]	transitions[0x0=>0x1]	509422	1			T1	191		T2	149		T13	165
all_pins[0]	transitions[0x1=>0x0]	65	1			T28	2		T176	2		T177	4
all_pins[1]	values[0x0]	101180004	1			T1	174225		T2	1610		T3	83
all_pins[1]	values[0x1]	79	1			T28	2		T176	2		T177	4
all_pins[1]	transitions[0x0=>0x1]	67	1			T28	2		T176	2		T177	4
all_pins[1]	transitions[0x1=>0x0]	323109	1			T23	1829		T32	990		T28	3601
all_pins[2]	values[0x0]	100856962	1			T1	174225		T2	1610		T3	83
all_pins[2]	values[0x1]	323121	1			T23	1829		T32	990		T28	3601
all_pins[2]	transitions[0x0=>0x1]	321190	1			T23	1817		T32	989		T28	3585
all_pins[2]	transitions[0x1=>0x0]	507523	1			T1	191		T2	149		T13	165