Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10855890 |
1 |
|
|
T1 |
19857 |
|
T2 |
16536 |
|
T3 |
2426 |
auto[1] |
25902618 |
1 |
|
|
T1 |
29126 |
|
T2 |
23818 |
|
T3 |
5542 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
36639283 |
1 |
|
|
T1 |
48880 |
|
T2 |
40272 |
|
T3 |
7968 |
triple_byte_access |
39704 |
1 |
|
|
T1 |
44 |
|
T2 |
29 |
|
T13 |
38 |
halfword_access |
40042 |
1 |
|
|
T1 |
29 |
|
T2 |
25 |
|
T13 |
16 |
byte_access |
39479 |
1 |
|
|
T1 |
30 |
|
T2 |
28 |
|
T13 |
22 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10736665 |
1 |
|
|
T1 |
19754 |
|
T2 |
16454 |
|
T3 |
2426 |
auto[0] |
triple_byte_access |
39704 |
1 |
|
|
T1 |
44 |
|
T2 |
29 |
|
T13 |
38 |
auto[0] |
halfword_access |
40042 |
1 |
|
|
T1 |
29 |
|
T2 |
25 |
|
T13 |
16 |
auto[0] |
byte_access |
39479 |
1 |
|
|
T1 |
30 |
|
T2 |
28 |
|
T13 |
22 |
auto[1] |
word_access |
25902618 |
1 |
|
|
T1 |
29126 |
|
T2 |
23818 |
|
T3 |
5542 |