Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.31 96.18 92.42 100.00 88.64 94.52 98.84 96.60


Total test records in report: 1238
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html
T1062 /workspace/coverage/default/0.kmac_alert_test.3960655825 Mar 19 01:03:37 PM PDT 24 Mar 19 01:03:42 PM PDT 24 83694588 ps
T1063 /workspace/coverage/default/2.kmac_entropy_refresh.1836943067 Mar 19 01:03:46 PM PDT 24 Mar 19 01:07:49 PM PDT 24 55380233553 ps
T1064 /workspace/coverage/default/36.kmac_long_msg_and_output.649902912 Mar 19 01:08:21 PM PDT 24 Mar 19 01:46:30 PM PDT 24 113681030233 ps
T1065 /workspace/coverage/default/4.kmac_entropy_ready_error.4006474132 Mar 19 01:03:59 PM PDT 24 Mar 19 01:04:46 PM PDT 24 30160156935 ps
T1066 /workspace/coverage/default/40.kmac_key_error.4070581616 Mar 19 01:09:32 PM PDT 24 Mar 19 01:09:38 PM PDT 24 3784342117 ps
T1067 /workspace/coverage/default/16.kmac_test_vectors_sha3_256.1455000378 Mar 19 01:05:21 PM PDT 24 Mar 19 01:30:18 PM PDT 24 18061501659 ps
T1068 /workspace/coverage/default/21.kmac_test_vectors_sha3_512.1916033404 Mar 19 01:05:43 PM PDT 24 Mar 19 01:20:42 PM PDT 24 131844014059 ps
T1069 /workspace/coverage/default/23.kmac_test_vectors_shake_128.3683877426 Mar 19 01:06:02 PM PDT 24 Mar 19 02:27:52 PM PDT 24 717763673432 ps
T1070 /workspace/coverage/default/29.kmac_test_vectors_sha3_512.3004735212 Mar 19 01:07:00 PM PDT 24 Mar 19 01:20:17 PM PDT 24 39945532733 ps
T1071 /workspace/coverage/default/34.kmac_lc_escalation.1970080365 Mar 19 01:07:57 PM PDT 24 Mar 19 01:07:59 PM PDT 24 99661198 ps
T1072 /workspace/coverage/default/18.kmac_key_error.765596671 Mar 19 01:05:19 PM PDT 24 Mar 19 01:05:23 PM PDT 24 646167532 ps
T1073 /workspace/coverage/default/28.kmac_lc_escalation.4074630343 Mar 19 01:06:49 PM PDT 24 Mar 19 01:06:53 PM PDT 24 146381410 ps
T1074 /workspace/coverage/default/48.kmac_test_vectors_sha3_384.206168143 Mar 19 01:12:01 PM PDT 24 Mar 19 01:31:21 PM PDT 24 54897229071 ps
T1075 /workspace/coverage/default/20.kmac_burst_write.931248366 Mar 19 01:05:43 PM PDT 24 Mar 19 01:14:51 PM PDT 24 76130861741 ps
T1076 /workspace/coverage/default/9.kmac_mubi.3226576134 Mar 19 01:04:27 PM PDT 24 Mar 19 01:07:43 PM PDT 24 6086280927 ps
T1077 /workspace/coverage/default/12.kmac_test_vectors_sha3_256.874395206 Mar 19 01:04:45 PM PDT 24 Mar 19 01:27:51 PM PDT 24 36358329449 ps
T1078 /workspace/coverage/default/9.kmac_error.1700446408 Mar 19 01:04:27 PM PDT 24 Mar 19 01:04:59 PM PDT 24 520120008 ps
T1079 /workspace/coverage/default/45.kmac_test_vectors_sha3_224.2929167246 Mar 19 01:10:56 PM PDT 24 Mar 19 01:35:19 PM PDT 24 19150801139 ps
T1080 /workspace/coverage/default/15.kmac_sideload.2655370360 Mar 19 01:05:05 PM PDT 24 Mar 19 01:05:21 PM PDT 24 2539832190 ps
T1081 /workspace/coverage/default/4.kmac_test_vectors_sha3_512.645027067 Mar 19 01:03:57 PM PDT 24 Mar 19 01:19:40 PM PDT 24 219018653931 ps
T1082 /workspace/coverage/default/33.kmac_smoke.990906055 Mar 19 01:07:46 PM PDT 24 Mar 19 01:08:31 PM PDT 24 859290729 ps
T1083 /workspace/coverage/default/0.kmac_lc_escalation.2151346655 Mar 19 01:03:37 PM PDT 24 Mar 19 01:03:43 PM PDT 24 153065690 ps
T1084 /workspace/coverage/default/17.kmac_long_msg_and_output.2725933525 Mar 19 01:05:15 PM PDT 24 Mar 19 01:13:34 PM PDT 24 11237610361 ps
T97 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.11319784 Mar 19 12:28:19 PM PDT 24 Mar 19 12:28:21 PM PDT 24 33074864 ps
T181 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.3293045998 Mar 19 12:29:00 PM PDT 24 Mar 19 12:29:01 PM PDT 24 51567807 ps
T136 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1593999190 Mar 19 12:28:13 PM PDT 24 Mar 19 12:28:14 PM PDT 24 101460189 ps
T182 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.1376583843 Mar 19 12:28:37 PM PDT 24 Mar 19 12:28:38 PM PDT 24 28213871 ps
T98 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.838388037 Mar 19 12:28:19 PM PDT 24 Mar 19 12:28:21 PM PDT 24 43728706 ps
T117 /workspace/coverage/cover_reg_top/23.kmac_intr_test.2975405648 Mar 19 12:28:42 PM PDT 24 Mar 19 12:28:43 PM PDT 24 18358442 ps
T118 /workspace/coverage/cover_reg_top/4.kmac_intr_test.3779611491 Mar 19 12:28:39 PM PDT 24 Mar 19 12:28:40 PM PDT 24 188066156 ps
T183 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2155533510 Mar 19 12:28:39 PM PDT 24 Mar 19 12:28:40 PM PDT 24 25702887 ps
T119 /workspace/coverage/cover_reg_top/37.kmac_intr_test.2951302242 Mar 19 12:28:43 PM PDT 24 Mar 19 12:28:44 PM PDT 24 19891375 ps
T124 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.101771824 Mar 19 12:28:15 PM PDT 24 Mar 19 12:28:18 PM PDT 24 329459503 ps
T1085 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.3713539322 Mar 19 12:29:12 PM PDT 24 Mar 19 12:29:14 PM PDT 24 10333520 ps
T109 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1209117892 Mar 19 12:28:15 PM PDT 24 Mar 19 12:28:16 PM PDT 24 16845078 ps
T125 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.579428751 Mar 19 12:28:47 PM PDT 24 Mar 19 12:28:48 PM PDT 24 32935033 ps
T142 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.4185753680 Mar 19 12:28:15 PM PDT 24 Mar 19 12:28:20 PM PDT 24 271253808 ps
T126 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1828851889 Mar 19 12:28:47 PM PDT 24 Mar 19 12:28:49 PM PDT 24 86581001 ps
T99 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.239940678 Mar 19 12:28:42 PM PDT 24 Mar 19 12:28:44 PM PDT 24 48423882 ps
T143 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3213319036 Mar 19 12:28:12 PM PDT 24 Mar 19 12:28:32 PM PDT 24 1487384236 ps
T127 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.58418877 Mar 19 12:28:48 PM PDT 24 Mar 19 12:28:49 PM PDT 24 82663172 ps
T1086 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3493530321 Mar 19 12:28:42 PM PDT 24 Mar 19 12:28:44 PM PDT 24 36627767 ps
T121 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.775162435 Mar 19 12:28:16 PM PDT 24 Mar 19 12:28:17 PM PDT 24 14574901 ps
T114 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3923707225 Mar 19 12:28:34 PM PDT 24 Mar 19 12:28:37 PM PDT 24 79050655 ps
T115 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3750653868 Mar 19 12:28:33 PM PDT 24 Mar 19 12:28:39 PM PDT 24 320109004 ps
T134 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.315640813 Mar 19 12:28:42 PM PDT 24 Mar 19 12:28:44 PM PDT 24 21070218 ps
T116 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1444019852 Mar 19 12:28:38 PM PDT 24 Mar 19 12:28:43 PM PDT 24 309412701 ps
T1087 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3445725917 Mar 19 12:28:59 PM PDT 24 Mar 19 12:29:00 PM PDT 24 10065631 ps
T159 /workspace/coverage/cover_reg_top/46.kmac_intr_test.2474352808 Mar 19 12:29:08 PM PDT 24 Mar 19 12:29:10 PM PDT 24 15683687 ps
T103 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.4101632167 Mar 19 12:28:32 PM PDT 24 Mar 19 12:28:35 PM PDT 24 139027694 ps
T167 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3373389834 Mar 19 12:28:52 PM PDT 24 Mar 19 12:28:54 PM PDT 24 63725327 ps
T1088 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.2052657341 Mar 19 12:28:49 PM PDT 24 Mar 19 12:28:51 PM PDT 24 18096775 ps
T147 /workspace/coverage/cover_reg_top/34.kmac_intr_test.3796256147 Mar 19 12:29:14 PM PDT 24 Mar 19 12:29:16 PM PDT 24 23500942 ps
T1089 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2669917334 Mar 19 12:29:15 PM PDT 24 Mar 19 12:29:18 PM PDT 24 62003238 ps
T144 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.988643993 Mar 19 12:28:55 PM PDT 24 Mar 19 12:28:57 PM PDT 24 64718863 ps
T1090 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3034408531 Mar 19 12:28:15 PM PDT 24 Mar 19 12:28:18 PM PDT 24 158633380 ps
T161 /workspace/coverage/cover_reg_top/28.kmac_intr_test.2588817924 Mar 19 12:28:45 PM PDT 24 Mar 19 12:28:46 PM PDT 24 13840172 ps
T100 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.121662816 Mar 19 12:29:34 PM PDT 24 Mar 19 12:29:37 PM PDT 24 347160031 ps
T113 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2974845341 Mar 19 12:28:18 PM PDT 24 Mar 19 12:28:21 PM PDT 24 64685746 ps
T145 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.98414612 Mar 19 12:28:42 PM PDT 24 Mar 19 12:28:44 PM PDT 24 247564139 ps
T146 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.3422944206 Mar 19 12:28:16 PM PDT 24 Mar 19 12:28:36 PM PDT 24 1262063352 ps
T1091 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.4047071115 Mar 19 12:28:42 PM PDT 24 Mar 19 12:28:45 PM PDT 24 33663223 ps
T1092 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.318896502 Mar 19 12:28:13 PM PDT 24 Mar 19 12:28:29 PM PDT 24 579309960 ps
T1093 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.791464074 Mar 19 12:28:43 PM PDT 24 Mar 19 12:28:44 PM PDT 24 51207888 ps
T1094 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.3808240275 Mar 19 12:28:17 PM PDT 24 Mar 19 12:28:19 PM PDT 24 224843601 ps
T101 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.4073798066 Mar 19 12:28:58 PM PDT 24 Mar 19 12:29:02 PM PDT 24 578023525 ps
T148 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.2073021303 Mar 19 12:28:51 PM PDT 24 Mar 19 12:28:54 PM PDT 24 290117136 ps
T1095 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3285719831 Mar 19 12:29:25 PM PDT 24 Mar 19 12:29:27 PM PDT 24 104416291 ps
T1096 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.2509716614 Mar 19 12:28:19 PM PDT 24 Mar 19 12:28:22 PM PDT 24 142024531 ps
T162 /workspace/coverage/cover_reg_top/20.kmac_intr_test.2903185410 Mar 19 12:28:35 PM PDT 24 Mar 19 12:28:37 PM PDT 24 42498468 ps
T105 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.11848255 Mar 19 12:28:36 PM PDT 24 Mar 19 12:28:38 PM PDT 24 51567128 ps
T163 /workspace/coverage/cover_reg_top/45.kmac_intr_test.2429992776 Mar 19 12:28:58 PM PDT 24 Mar 19 12:28:59 PM PDT 24 102910996 ps
T1097 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2193076016 Mar 19 12:28:16 PM PDT 24 Mar 19 12:28:18 PM PDT 24 302840511 ps
T1098 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.1825938653 Mar 19 12:29:21 PM PDT 24 Mar 19 12:29:23 PM PDT 24 345581005 ps
T1099 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3633370179 Mar 19 12:29:02 PM PDT 24 Mar 19 12:29:04 PM PDT 24 118954868 ps
T1100 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.1656131084 Mar 19 12:28:15 PM PDT 24 Mar 19 12:28:24 PM PDT 24 402157484 ps
T1101 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1811725960 Mar 19 12:29:02 PM PDT 24 Mar 19 12:29:03 PM PDT 24 17517519 ps
T1102 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.1706198472 Mar 19 12:28:46 PM PDT 24 Mar 19 12:28:48 PM PDT 24 26925051 ps
T175 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.4059205617 Mar 19 12:29:01 PM PDT 24 Mar 19 12:29:07 PM PDT 24 1008185862 ps
T1103 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2490951262 Mar 19 12:28:14 PM PDT 24 Mar 19 12:28:17 PM PDT 24 288058793 ps
T102 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3994353007 Mar 19 12:28:54 PM PDT 24 Mar 19 12:28:56 PM PDT 24 112558463 ps
T108 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1086273599 Mar 19 12:28:13 PM PDT 24 Mar 19 12:28:16 PM PDT 24 56236798 ps
T1104 /workspace/coverage/cover_reg_top/0.kmac_intr_test.2079585840 Mar 19 12:29:37 PM PDT 24 Mar 19 12:29:37 PM PDT 24 28946998 ps
T1105 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.1913945012 Mar 19 12:28:40 PM PDT 24 Mar 19 12:28:42 PM PDT 24 19033084 ps
T1106 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.3275660296 Mar 19 12:29:31 PM PDT 24 Mar 19 12:29:32 PM PDT 24 34250063 ps
T1107 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.3214435569 Mar 19 12:28:24 PM PDT 24 Mar 19 12:28:25 PM PDT 24 97020519 ps
T1108 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2277844749 Mar 19 12:28:13 PM PDT 24 Mar 19 12:28:15 PM PDT 24 229287895 ps
T1109 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1487849060 Mar 19 12:28:31 PM PDT 24 Mar 19 12:28:41 PM PDT 24 1257708187 ps
T1110 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.1034613115 Mar 19 12:28:55 PM PDT 24 Mar 19 12:28:58 PM PDT 24 86059752 ps
T164 /workspace/coverage/cover_reg_top/26.kmac_intr_test.1079133428 Mar 19 12:28:43 PM PDT 24 Mar 19 12:28:43 PM PDT 24 32125959 ps
T169 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3513643253 Mar 19 12:29:14 PM PDT 24 Mar 19 12:29:20 PM PDT 24 2024336026 ps
T1111 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2713226715 Mar 19 12:28:16 PM PDT 24 Mar 19 12:28:18 PM PDT 24 27562234 ps
T1112 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.2073565828 Mar 19 12:28:36 PM PDT 24 Mar 19 12:28:37 PM PDT 24 74371270 ps
T1113 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.3300000863 Mar 19 12:28:30 PM PDT 24 Mar 19 12:28:31 PM PDT 24 63094473 ps
T165 /workspace/coverage/cover_reg_top/33.kmac_intr_test.2568026014 Mar 19 12:28:45 PM PDT 24 Mar 19 12:28:46 PM PDT 24 21292162 ps
T1114 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.993610505 Mar 19 12:28:15 PM PDT 24 Mar 19 12:28:27 PM PDT 24 47587177 ps
T160 /workspace/coverage/cover_reg_top/6.kmac_intr_test.113887225 Mar 19 12:28:16 PM PDT 24 Mar 19 12:28:17 PM PDT 24 46573832 ps
T1115 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1170054942 Mar 19 12:29:09 PM PDT 24 Mar 19 12:29:10 PM PDT 24 16299217 ps
T1116 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.2629524580 Mar 19 12:29:22 PM PDT 24 Mar 19 12:29:23 PM PDT 24 50707986 ps
T1117 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3098985896 Mar 19 12:29:19 PM PDT 24 Mar 19 12:29:21 PM PDT 24 105844128 ps
T104 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1837643676 Mar 19 12:28:45 PM PDT 24 Mar 19 12:28:46 PM PDT 24 51712751 ps
T1118 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.474702888 Mar 19 12:28:32 PM PDT 24 Mar 19 12:28:34 PM PDT 24 276141408 ps
T1119 /workspace/coverage/cover_reg_top/13.kmac_intr_test.4134237660 Mar 19 12:28:37 PM PDT 24 Mar 19 12:28:38 PM PDT 24 15490707 ps
T1120 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.3649120502 Mar 19 12:28:37 PM PDT 24 Mar 19 12:28:38 PM PDT 24 47593871 ps
T170 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2912776368 Mar 19 12:28:12 PM PDT 24 Mar 19 12:28:15 PM PDT 24 105866678 ps
T106 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2396048106 Mar 19 12:28:16 PM PDT 24 Mar 19 12:28:19 PM PDT 24 472467474 ps
T1121 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2294173580 Mar 19 12:28:18 PM PDT 24 Mar 19 12:28:25 PM PDT 24 52555264 ps
T137 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1856549564 Mar 19 12:28:31 PM PDT 24 Mar 19 12:28:33 PM PDT 24 44186146 ps
T1122 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.239756158 Mar 19 12:29:38 PM PDT 24 Mar 19 12:29:40 PM PDT 24 198063847 ps
T1123 /workspace/coverage/cover_reg_top/15.kmac_intr_test.1424355901 Mar 19 12:28:51 PM PDT 24 Mar 19 12:28:52 PM PDT 24 24014635 ps
T171 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.4251450023 Mar 19 12:28:55 PM PDT 24 Mar 19 12:29:00 PM PDT 24 833272771 ps
T1124 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3733192212 Mar 19 12:28:23 PM PDT 24 Mar 19 12:28:25 PM PDT 24 69470644 ps
T1125 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3508209706 Mar 19 12:28:36 PM PDT 24 Mar 19 12:28:38 PM PDT 24 245183727 ps
T107 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3840133908 Mar 19 12:29:09 PM PDT 24 Mar 19 12:29:10 PM PDT 24 106071573 ps
T166 /workspace/coverage/cover_reg_top/31.kmac_intr_test.2151179919 Mar 19 12:28:35 PM PDT 24 Mar 19 12:28:37 PM PDT 24 52312563 ps
T168 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3518188689 Mar 19 12:28:13 PM PDT 24 Mar 19 12:28:18 PM PDT 24 562870237 ps
T1126 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.2916078150 Mar 19 12:28:18 PM PDT 24 Mar 19 12:28:20 PM PDT 24 99909445 ps
T1127 /workspace/coverage/cover_reg_top/16.kmac_intr_test.1218416757 Mar 19 12:29:38 PM PDT 24 Mar 19 12:29:39 PM PDT 24 13872848 ps
T1128 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2747429444 Mar 19 12:28:26 PM PDT 24 Mar 19 12:28:27 PM PDT 24 103615432 ps
T1129 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.204516044 Mar 19 12:29:39 PM PDT 24 Mar 19 12:29:41 PM PDT 24 133191728 ps
T1130 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2123007642 Mar 19 12:28:15 PM PDT 24 Mar 19 12:28:17 PM PDT 24 65421086 ps
T1131 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.337792107 Mar 19 12:28:06 PM PDT 24 Mar 19 12:28:08 PM PDT 24 121452819 ps
T1132 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.13862968 Mar 19 12:28:41 PM PDT 24 Mar 19 12:28:43 PM PDT 24 91281364 ps
T1133 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.1294013642 Mar 19 12:28:14 PM PDT 24 Mar 19 12:28:16 PM PDT 24 27277802 ps
T1134 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3095751696 Mar 19 12:29:12 PM PDT 24 Mar 19 12:29:15 PM PDT 24 125880430 ps
T1135 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2132314066 Mar 19 12:28:14 PM PDT 24 Mar 19 12:28:16 PM PDT 24 32116455 ps
T172 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2435369952 Mar 19 12:29:16 PM PDT 24 Mar 19 12:29:21 PM PDT 24 819068408 ps
T1136 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2612165768 Mar 19 12:28:25 PM PDT 24 Mar 19 12:28:27 PM PDT 24 78095357 ps
T1137 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.2955404531 Mar 19 12:28:23 PM PDT 24 Mar 19 12:28:26 PM PDT 24 89096491 ps
T1138 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3513743328 Mar 19 12:29:37 PM PDT 24 Mar 19 12:29:38 PM PDT 24 40578120 ps
T1139 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.4242469660 Mar 19 12:28:25 PM PDT 24 Mar 19 12:28:28 PM PDT 24 161332460 ps
T1140 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.1860338184 Mar 19 12:28:42 PM PDT 24 Mar 19 12:28:44 PM PDT 24 49569737 ps
T1141 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.3534360922 Mar 19 12:28:43 PM PDT 24 Mar 19 12:28:46 PM PDT 24 87240368 ps
T138 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.2342066199 Mar 19 12:28:40 PM PDT 24 Mar 19 12:28:42 PM PDT 24 56062776 ps
T139 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.1211110106 Mar 19 12:28:11 PM PDT 24 Mar 19 12:28:12 PM PDT 24 33624288 ps
T1142 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.3519272453 Mar 19 12:28:30 PM PDT 24 Mar 19 12:28:32 PM PDT 24 113969524 ps
T1143 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1961414804 Mar 19 12:28:18 PM PDT 24 Mar 19 12:28:20 PM PDT 24 375633897 ps
T1144 /workspace/coverage/cover_reg_top/49.kmac_intr_test.3657401234 Mar 19 12:28:51 PM PDT 24 Mar 19 12:28:52 PM PDT 24 27803284 ps
T1145 /workspace/coverage/cover_reg_top/17.kmac_intr_test.3989907119 Mar 19 12:29:22 PM PDT 24 Mar 19 12:29:23 PM PDT 24 45212491 ps
T1146 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.826340897 Mar 19 12:28:10 PM PDT 24 Mar 19 12:28:12 PM PDT 24 45331974 ps
T1147 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2752375241 Mar 19 12:28:30 PM PDT 24 Mar 19 12:28:33 PM PDT 24 168373970 ps
T1148 /workspace/coverage/cover_reg_top/14.kmac_intr_test.699957745 Mar 19 12:28:21 PM PDT 24 Mar 19 12:28:21 PM PDT 24 21094953 ps
T1149 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.421316462 Mar 19 12:28:48 PM PDT 24 Mar 19 12:28:51 PM PDT 24 153296437 ps
T1150 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2806454455 Mar 19 12:28:16 PM PDT 24 Mar 19 12:28:18 PM PDT 24 68764560 ps
T1151 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1667048849 Mar 19 12:28:45 PM PDT 24 Mar 19 12:28:47 PM PDT 24 59116248 ps
T1152 /workspace/coverage/cover_reg_top/44.kmac_intr_test.496872363 Mar 19 12:28:39 PM PDT 24 Mar 19 12:28:41 PM PDT 24 21409378 ps
T1153 /workspace/coverage/cover_reg_top/24.kmac_intr_test.2348011697 Mar 19 12:28:52 PM PDT 24 Mar 19 12:28:53 PM PDT 24 17359793 ps
T1154 /workspace/coverage/cover_reg_top/42.kmac_intr_test.1774615215 Mar 19 12:28:46 PM PDT 24 Mar 19 12:28:47 PM PDT 24 11223347 ps
T1155 /workspace/coverage/cover_reg_top/36.kmac_intr_test.3474775548 Mar 19 12:28:44 PM PDT 24 Mar 19 12:28:46 PM PDT 24 22007354 ps
T1156 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.4269081282 Mar 19 12:28:53 PM PDT 24 Mar 19 12:28:56 PM PDT 24 603037821 ps
T1157 /workspace/coverage/cover_reg_top/21.kmac_intr_test.824587894 Mar 19 12:28:45 PM PDT 24 Mar 19 12:28:46 PM PDT 24 13364805 ps
T1158 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3041208307 Mar 19 12:28:39 PM PDT 24 Mar 19 12:28:41 PM PDT 24 80628789 ps
T1159 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3385765388 Mar 19 12:28:21 PM PDT 24 Mar 19 12:28:24 PM PDT 24 427994702 ps
T1160 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2863875592 Mar 19 12:28:43 PM PDT 24 Mar 19 12:28:46 PM PDT 24 124135004 ps
T1161 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2799494683 Mar 19 12:29:03 PM PDT 24 Mar 19 12:29:04 PM PDT 24 489616439 ps
T1162 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.26858002 Mar 19 12:29:12 PM PDT 24 Mar 19 12:29:22 PM PDT 24 158200877 ps
T1163 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2289695821 Mar 19 12:28:42 PM PDT 24 Mar 19 12:28:45 PM PDT 24 120125785 ps
T1164 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3967343782 Mar 19 12:28:02 PM PDT 24 Mar 19 12:28:04 PM PDT 24 365228033 ps
T1165 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.295158193 Mar 19 12:28:35 PM PDT 24 Mar 19 12:28:38 PM PDT 24 136462020 ps
T1166 /workspace/coverage/cover_reg_top/35.kmac_intr_test.3252937489 Mar 19 12:28:42 PM PDT 24 Mar 19 12:28:43 PM PDT 24 24059447 ps
T1167 /workspace/coverage/cover_reg_top/27.kmac_intr_test.1293532221 Mar 19 12:28:44 PM PDT 24 Mar 19 12:28:45 PM PDT 24 11895580 ps
T1168 /workspace/coverage/cover_reg_top/5.kmac_intr_test.688500511 Mar 19 12:28:12 PM PDT 24 Mar 19 12:28:13 PM PDT 24 60477050 ps
T1169 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.3490833555 Mar 19 12:29:02 PM PDT 24 Mar 19 12:29:05 PM PDT 24 526627697 ps
T1170 /workspace/coverage/cover_reg_top/8.kmac_intr_test.2706551689 Mar 19 12:28:37 PM PDT 24 Mar 19 12:28:38 PM PDT 24 14426008 ps
T180 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.132823253 Mar 19 12:28:38 PM PDT 24 Mar 19 12:28:42 PM PDT 24 109234066 ps
T1171 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2574158148 Mar 19 12:28:31 PM PDT 24 Mar 19 12:28:32 PM PDT 24 36577808 ps
T1172 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1891395277 Mar 19 12:28:42 PM PDT 24 Mar 19 12:28:44 PM PDT 24 196117449 ps
T1173 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.536040728 Mar 19 12:29:18 PM PDT 24 Mar 19 12:29:20 PM PDT 24 103648704 ps
T1174 /workspace/coverage/cover_reg_top/12.kmac_intr_test.1966311141 Mar 19 12:28:45 PM PDT 24 Mar 19 12:28:46 PM PDT 24 48246777 ps
T1175 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.801916633 Mar 19 12:28:14 PM PDT 24 Mar 19 12:28:16 PM PDT 24 37245811 ps
T1176 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2265886780 Mar 19 12:28:16 PM PDT 24 Mar 19 12:28:18 PM PDT 24 228864601 ps
T1177 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.2114482340 Mar 19 12:28:42 PM PDT 24 Mar 19 12:28:44 PM PDT 24 177737233 ps
T1178 /workspace/coverage/cover_reg_top/47.kmac_intr_test.900557866 Mar 19 12:28:54 PM PDT 24 Mar 19 12:28:55 PM PDT 24 46898016 ps
T1179 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3844790217 Mar 19 12:28:13 PM PDT 24 Mar 19 12:28:16 PM PDT 24 388709381 ps
T1180 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.828110051 Mar 19 12:28:37 PM PDT 24 Mar 19 12:28:40 PM PDT 24 103514235 ps
T1181 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2194592083 Mar 19 12:28:38 PM PDT 24 Mar 19 12:28:55 PM PDT 24 49581921 ps
T1182 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.812566375 Mar 19 12:29:17 PM PDT 24 Mar 19 12:29:19 PM PDT 24 35104147 ps
T1183 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3765708085 Mar 19 12:28:43 PM PDT 24 Mar 19 12:28:45 PM PDT 24 74887735 ps
T1184 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2241963851 Mar 19 12:28:43 PM PDT 24 Mar 19 12:28:46 PM PDT 24 276885544 ps
T1185 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.148812690 Mar 19 12:29:13 PM PDT 24 Mar 19 12:29:16 PM PDT 24 121676050 ps
T1186 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.722749185 Mar 19 12:28:35 PM PDT 24 Mar 19 12:28:37 PM PDT 24 26994775 ps
T1187 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.673014466 Mar 19 12:28:44 PM PDT 24 Mar 19 12:28:45 PM PDT 24 249861733 ps
T1188 /workspace/coverage/cover_reg_top/38.kmac_intr_test.2613084968 Mar 19 12:28:53 PM PDT 24 Mar 19 12:28:54 PM PDT 24 13756997 ps
T1189 /workspace/coverage/cover_reg_top/18.kmac_intr_test.2058997068 Mar 19 12:28:43 PM PDT 24 Mar 19 12:28:48 PM PDT 24 48737676 ps
T1190 /workspace/coverage/cover_reg_top/2.kmac_intr_test.52829164 Mar 19 12:28:10 PM PDT 24 Mar 19 12:28:11 PM PDT 24 24494315 ps
T1191 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.4256452594 Mar 19 12:29:02 PM PDT 24 Mar 19 12:29:03 PM PDT 24 41467754 ps
T1192 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.3850325368 Mar 19 12:28:16 PM PDT 24 Mar 19 12:28:17 PM PDT 24 62744720 ps
T1193 /workspace/coverage/cover_reg_top/43.kmac_intr_test.2471476682 Mar 19 12:28:50 PM PDT 24 Mar 19 12:28:52 PM PDT 24 60528168 ps
T1194 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.1962488514 Mar 19 12:28:54 PM PDT 24 Mar 19 12:28:57 PM PDT 24 399422728 ps
T1195 /workspace/coverage/cover_reg_top/48.kmac_intr_test.2476611961 Mar 19 12:28:36 PM PDT 24 Mar 19 12:28:37 PM PDT 24 45549236 ps
T1196 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.807764344 Mar 19 12:28:25 PM PDT 24 Mar 19 12:28:28 PM PDT 24 139579439 ps
T1197 /workspace/coverage/cover_reg_top/19.kmac_intr_test.3507453146 Mar 19 12:29:02 PM PDT 24 Mar 19 12:29:03 PM PDT 24 12801867 ps
T1198 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2050679677 Mar 19 12:28:49 PM PDT 24 Mar 19 12:28:51 PM PDT 24 24286414 ps
T1199 /workspace/coverage/cover_reg_top/11.kmac_intr_test.1326157915 Mar 19 12:28:34 PM PDT 24 Mar 19 12:28:37 PM PDT 24 15637844 ps
T1200 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3287213470 Mar 19 12:28:42 PM PDT 24 Mar 19 12:28:45 PM PDT 24 98820348 ps
T120 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.624392287 Mar 19 12:28:53 PM PDT 24 Mar 19 12:28:56 PM PDT 24 498623050 ps
T1201 /workspace/coverage/cover_reg_top/7.kmac_intr_test.2049137352 Mar 19 12:28:32 PM PDT 24 Mar 19 12:28:34 PM PDT 24 14149858 ps
T1202 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.4032671729 Mar 19 12:28:33 PM PDT 24 Mar 19 12:28:44 PM PDT 24 3475690967 ps
T1203 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.496845734 Mar 19 12:28:36 PM PDT 24 Mar 19 12:28:39 PM PDT 24 181238528 ps
T1204 /workspace/coverage/cover_reg_top/32.kmac_intr_test.3041980071 Mar 19 12:29:19 PM PDT 24 Mar 19 12:29:20 PM PDT 24 19662875 ps
T1205 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3912640537 Mar 19 12:28:48 PM PDT 24 Mar 19 12:28:51 PM PDT 24 75956710 ps
T1206 /workspace/coverage/cover_reg_top/9.kmac_intr_test.3053029561 Mar 19 12:28:44 PM PDT 24 Mar 19 12:28:46 PM PDT 24 16473808 ps
T1207 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2202473857 Mar 19 12:28:31 PM PDT 24 Mar 19 12:28:33 PM PDT 24 69009688 ps
T1208 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1034108098 Mar 19 12:29:17 PM PDT 24 Mar 19 12:29:19 PM PDT 24 191219485 ps
T1209 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3660294881 Mar 19 12:28:47 PM PDT 24 Mar 19 12:28:51 PM PDT 24 354553193 ps
T1210 /workspace/coverage/cover_reg_top/39.kmac_intr_test.3518212053 Mar 19 12:28:38 PM PDT 24 Mar 19 12:28:39 PM PDT 24 20012719 ps
T1211 /workspace/coverage/cover_reg_top/1.kmac_intr_test.1837984328 Mar 19 12:28:26 PM PDT 24 Mar 19 12:28:27 PM PDT 24 125637029 ps
T1212 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.3684443093 Mar 19 12:28:40 PM PDT 24 Mar 19 12:28:42 PM PDT 24 46750812 ps
T1213 /workspace/coverage/cover_reg_top/29.kmac_intr_test.3817032806 Mar 19 12:28:28 PM PDT 24 Mar 19 12:28:29 PM PDT 24 15112192 ps
T1214 /workspace/coverage/cover_reg_top/25.kmac_intr_test.2400733257 Mar 19 12:29:07 PM PDT 24 Mar 19 12:29:08 PM PDT 24 27894645 ps
T1215 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.1090614057 Mar 19 12:28:37 PM PDT 24 Mar 19 12:28:39 PM PDT 24 93532583 ps
T1216 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.555251209 Mar 19 12:28:15 PM PDT 24 Mar 19 12:28:17 PM PDT 24 50538093 ps
T1217 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1758620502 Mar 19 12:28:22 PM PDT 24 Mar 19 12:28:23 PM PDT 24 26102718 ps
T1218 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2505850000 Mar 19 12:28:37 PM PDT 24 Mar 19 12:28:44 PM PDT 24 84062606 ps
T1219 /workspace/coverage/cover_reg_top/30.kmac_intr_test.2534378568 Mar 19 12:28:44 PM PDT 24 Mar 19 12:28:45 PM PDT 24 38744491 ps
T1220 /workspace/coverage/cover_reg_top/22.kmac_intr_test.1278624617 Mar 19 12:28:57 PM PDT 24 Mar 19 12:28:59 PM PDT 24 14209858 ps
T1221 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2543504591 Mar 19 12:29:20 PM PDT 24 Mar 19 12:29:22 PM PDT 24 32717238 ps
T1222 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3989393631 Mar 19 12:28:38 PM PDT 24 Mar 19 12:28:40 PM PDT 24 53815777 ps
T1223 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.577691950 Mar 19 12:28:48 PM PDT 24 Mar 19 12:28:51 PM PDT 24 103031338 ps
T140 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3983121086 Mar 19 12:28:31 PM PDT 24 Mar 19 12:28:33 PM PDT 24 42522486 ps
T1224 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1439510859 Mar 19 12:28:27 PM PDT 24 Mar 19 12:28:28 PM PDT 24 73802726 ps
T1225 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.4032256395 Mar 19 12:29:03 PM PDT 24 Mar 19 12:29:04 PM PDT 24 55556014 ps
T1226 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2900130381 Mar 19 12:28:28 PM PDT 24 Mar 19 12:28:38 PM PDT 24 1009643265 ps
T1227 /workspace/coverage/cover_reg_top/10.kmac_intr_test.940143141 Mar 19 12:28:29 PM PDT 24 Mar 19 12:28:30 PM PDT 24 14315414 ps
T1228 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2421460398 Mar 19 12:28:37 PM PDT 24 Mar 19 12:28:39 PM PDT 24 46869450 ps
T1229 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3891132319 Mar 19 12:28:40 PM PDT 24 Mar 19 12:28:43 PM PDT 24 133075309 ps
T1230 /workspace/coverage/cover_reg_top/41.kmac_intr_test.2110208759 Mar 19 12:28:58 PM PDT 24 Mar 19 12:29:00 PM PDT 24 13512058 ps
T1231 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1715170565 Mar 19 12:28:30 PM PDT 24 Mar 19 12:28:32 PM PDT 24 169857813 ps
T173 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.296170155 Mar 19 12:28:42 PM PDT 24 Mar 19 12:28:46 PM PDT 24 618487576 ps
T174 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.2120789058 Mar 19 12:28:14 PM PDT 24 Mar 19 12:28:20 PM PDT 24 906993260 ps
T179 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.4186544230 Mar 19 12:28:31 PM PDT 24 Mar 19 12:28:35 PM PDT 24 137636447 ps
T1232 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1652944927 Mar 19 12:29:05 PM PDT 24 Mar 19 12:29:07 PM PDT 24 110580232 ps
T1233 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1250512213 Mar 19 12:28:19 PM PDT 24 Mar 19 12:28:20 PM PDT 24 19524194 ps
T1234 /workspace/coverage/cover_reg_top/3.kmac_intr_test.4007042522 Mar 19 12:28:38 PM PDT 24 Mar 19 12:28:39 PM PDT 24 15892212 ps
T1235 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.631959592 Mar 19 12:28:31 PM PDT 24 Mar 19 12:28:32 PM PDT 24 47380336 ps
T1236 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1638872245 Mar 19 12:28:18 PM PDT 24 Mar 19 12:28:21 PM PDT 24 439272921 ps
T1237 /workspace/coverage/cover_reg_top/40.kmac_intr_test.793516655 Mar 19 12:28:44 PM PDT 24 Mar 19 12:28:46 PM PDT 24 22329345 ps
T1238 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2541725460 Mar 19 12:28:26 PM PDT 24 Mar 19 12:28:31 PM PDT 24 204192822 ps

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.2362064674
Short name T3
Test name
Test status
Simulation time 14466176279 ps
CPU time 30.36 seconds
Started Mar 19 01:03:47 PM PDT 24
Finished Mar 19 01:04:19 PM PDT 24
Peak memory 217232 kb
Host smart-bf83d0bf-7750-4f6f-b4ee-ae8295ab37fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362064674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2362064674 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/30.kmac_burst_write.1556562817
Short name T2
Test name
Test status
Simulation time 63245831541 ps
CPU time 437.56 seconds
Started Mar 19 01:07:07 PM PDT 24
Finished Mar 19 01:14:25 PM PDT 24
Peak memory 228176 kb
Host smart-a477714e-1837-4837-9165-456382c9a8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556562817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.1556562817 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_stress_all_with_rand_reset.809765639
Short name T29
Test name
Test status
Simulation time 234200264808 ps
CPU time 1739.67 seconds
Started Mar 19 01:06:49 PM PDT 24
Finished Mar 19 01:35:49 PM PDT 24
Peak memory 341504 kb
Host smart-7a2ed42b-bedb-4206-bf77-01144cf279f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=809765639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all_with_rand_reset.809765639 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3750653868
Short name T115
Test name
Test status
Simulation time 320109004 ps
CPU time 4.73 seconds
Started Mar 19 12:28:33 PM PDT 24
Finished Mar 19 12:28:39 PM PDT 24
Peak memory 214580 kb
Host smart-49cd7547-1319-492c-a3eb-c1b9ee3a408f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750653868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3750
653868 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.4140598098
Short name T6
Test name
Test status
Simulation time 41411502 ps
CPU time 1.41 seconds
Started Mar 19 01:04:08 PM PDT 24
Finished Mar 19 01:04:11 PM PDT 24
Peak memory 218096 kb
Host smart-846b5b6d-6cfb-428c-9b0b-9e9a06f63609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140598098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.4140598098 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.3059832724
Short name T10
Test name
Test status
Simulation time 1684903357 ps
CPU time 26.54 seconds
Started Mar 19 01:03:59 PM PDT 24
Finished Mar 19 01:04:25 PM PDT 24
Peak memory 241852 kb
Host smart-3413b6a0-d05e-4a85-816b-5da1a14015a6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059832724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.3059832724 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/32.kmac_key_error.1159930333
Short name T24
Test name
Test status
Simulation time 668318345 ps
CPU time 3.64 seconds
Started Mar 19 01:07:47 PM PDT 24
Finished Mar 19 01:07:51 PM PDT 24
Peak memory 207260 kb
Host smart-fed3049f-14bd-49f7-870d-97c9d1ec991f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159930333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.1159930333 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_error.2671384094
Short name T95
Test name
Test status
Simulation time 3023895490 ps
CPU time 227.11 seconds
Started Mar 19 01:11:57 PM PDT 24
Finished Mar 19 01:15:44 PM PDT 24
Peak memory 256872 kb
Host smart-20051e04-572a-4947-b8c0-f8ea03b0e2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671384094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.2671384094 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.519464734
Short name T83
Test name
Test status
Simulation time 196033445 ps
CPU time 2.94 seconds
Started Mar 19 01:09:31 PM PDT 24
Finished Mar 19 01:09:34 PM PDT 24
Peak memory 220244 kb
Host smart-63bda530-31b2-4970-93cc-4822ffdfbf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519464734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.519464734 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.2684495846
Short name T36
Test name
Test status
Simulation time 105284586 ps
CPU time 1.1 seconds
Started Mar 19 01:11:07 PM PDT 24
Finished Mar 19 01:11:09 PM PDT 24
Peak memory 215868 kb
Host smart-51c0bfd3-8c65-4855-b1c4-9f5800b34aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684495846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.2684495846 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3840133908
Short name T107
Test name
Test status
Simulation time 106071573 ps
CPU time 1.24 seconds
Started Mar 19 12:29:09 PM PDT 24
Finished Mar 19 12:29:10 PM PDT 24
Peak memory 214928 kb
Host smart-ca3c85c0-914b-4a42-a0d5-cf6bd14d263f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840133908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.3840133908 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.3654152443
Short name T35
Test name
Test status
Simulation time 145997011 ps
CPU time 1.22 seconds
Started Mar 19 01:12:15 PM PDT 24
Finished Mar 19 01:12:16 PM PDT 24
Peak memory 215896 kb
Host smart-2f03032b-9682-42e2-82be-336a4fbb54ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654152443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3654152443 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.3779611491
Short name T118
Test name
Test status
Simulation time 188066156 ps
CPU time 0.75 seconds
Started Mar 19 12:28:39 PM PDT 24
Finished Mar 19 12:28:40 PM PDT 24
Peak memory 206256 kb
Host smart-4296ee3f-9493-4c6b-a3c7-a905c5d7bec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779611491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3779611491 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/default/24.kmac_stress_all.4174167264
Short name T23
Test name
Test status
Simulation time 28075691085 ps
CPU time 601.24 seconds
Started Mar 19 01:06:14 PM PDT 24
Finished Mar 19 01:16:15 PM PDT 24
Peak memory 307100 kb
Host smart-6f99e3eb-954f-438e-9f4b-13e462f375f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4174167264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.4174167264 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.239940678
Short name T99
Test name
Test status
Simulation time 48423882 ps
CPU time 1.33 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:28:44 PM PDT 24
Peak memory 214960 kb
Host smart-2f63494b-43db-46d2-804d-e9a814b7af00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239940678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_e
rrors.239940678 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.1496877205
Short name T89
Test name
Test status
Simulation time 448517398367 ps
CPU time 4403.74 seconds
Started Mar 19 01:06:41 PM PDT 24
Finished Mar 19 02:20:05 PM PDT 24
Peak memory 555932 kb
Host smart-be05854d-8504-4ea1-8112-9bb9ac6f3197
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1496877205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.1496877205 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1593999190
Short name T136
Test name
Test status
Simulation time 101460189 ps
CPU time 1.21 seconds
Started Mar 19 12:28:13 PM PDT 24
Finished Mar 19 12:28:14 PM PDT 24
Peak memory 214596 kb
Host smart-b465ff02-9bcd-46ae-9f2b-07a3a77478a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593999190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.1593999190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/10.kmac_alert_test.3550526555
Short name T266
Test name
Test status
Simulation time 17664402 ps
CPU time 0.81 seconds
Started Mar 19 01:04:36 PM PDT 24
Finished Mar 19 01:04:37 PM PDT 24
Peak memory 205372 kb
Host smart-0309ae08-1063-4b83-8533-3d0773d25325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550526555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.3550526555 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.2120789058
Short name T174
Test name
Test status
Simulation time 906993260 ps
CPU time 4.59 seconds
Started Mar 19 12:28:14 PM PDT 24
Finished Mar 19 12:28:20 PM PDT 24
Peak memory 214564 kb
Host smart-882d03ec-fe40-45dd-978a-7e06a6dccacb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120789058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.21207
89058 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.2903185410
Short name T162
Test name
Test status
Simulation time 42498468 ps
CPU time 0.78 seconds
Started Mar 19 12:28:35 PM PDT 24
Finished Mar 19 12:28:37 PM PDT 24
Peak memory 206304 kb
Host smart-28984e1e-f101-4e88-b85e-480f2a5e7c2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903185410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2903185410 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.1544511006
Short name T157
Test name
Test status
Simulation time 52886037540 ps
CPU time 4137.44 seconds
Started Mar 19 01:03:40 PM PDT 24
Finished Mar 19 02:12:40 PM PDT 24
Peak memory 659516 kb
Host smart-2f82a398-cb23-4752-8dc7-68e36f62abb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1544511006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.1544511006 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_error.2903758143
Short name T153
Test name
Test status
Simulation time 50614874290 ps
CPU time 330.83 seconds
Started Mar 19 01:06:41 PM PDT 24
Finished Mar 19 01:12:12 PM PDT 24
Peak memory 256924 kb
Host smart-e221a88a-32ea-420a-a304-fbd3346aa337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903758143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.2903758143 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_stress_all.2622136082
Short name T84
Test name
Test status
Simulation time 61443775966 ps
CPU time 906.24 seconds
Started Mar 19 01:03:47 PM PDT 24
Finished Mar 19 01:18:53 PM PDT 24
Peak memory 336768 kb
Host smart-6bd4491a-737b-459d-879d-f8789488788d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2622136082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.2622136082 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3660294881
Short name T1209
Test name
Test status
Simulation time 354553193 ps
CPU time 4.56 seconds
Started Mar 19 12:28:47 PM PDT 24
Finished Mar 19 12:28:51 PM PDT 24
Peak memory 214636 kb
Host smart-0979b29e-ddcc-4041-bebb-043686ddcb9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660294881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3660
294881 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.1566581007
Short name T155
Test name
Test status
Simulation time 379947504107 ps
CPU time 4449.03 seconds
Started Mar 19 01:11:20 PM PDT 24
Finished Mar 19 02:25:30 PM PDT 24
Peak memory 568772 kb
Host smart-a41a6833-28ec-4c30-b0a2-78c4db16e5c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1566581007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.1566581007 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.2437931081
Short name T41
Test name
Test status
Simulation time 33750707025 ps
CPU time 74.25 seconds
Started Mar 19 01:04:19 PM PDT 24
Finished Mar 19 01:05:33 PM PDT 24
Peak memory 215980 kb
Host smart-013e02c7-20e0-45e8-927e-4cd02b694c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437931081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.2437931081 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.4073798066
Short name T101
Test name
Test status
Simulation time 578023525 ps
CPU time 2.55 seconds
Started Mar 19 12:28:58 PM PDT 24
Finished Mar 19 12:29:02 PM PDT 24
Peak memory 214856 kb
Host smart-e52af014-9437-440b-8422-0587053a2e28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073798066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.4073798066 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.kmac_stress_all.1734911553
Short name T453
Test name
Test status
Simulation time 50674763068 ps
CPU time 573.54 seconds
Started Mar 19 01:05:22 PM PDT 24
Finished Mar 19 01:14:56 PM PDT 24
Peak memory 299828 kb
Host smart-eea0d6e4-2949-4ee5-b9bd-57f71e84c554
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1734911553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.1734911553 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.624392287
Short name T120
Test name
Test status
Simulation time 498623050 ps
CPU time 2.62 seconds
Started Mar 19 12:28:53 PM PDT 24
Finished Mar 19 12:28:56 PM PDT 24
Peak memory 214844 kb
Host smart-be6d8ef5-d1b7-494a-81d5-639fa6586fde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624392287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.62439
2287 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.4032671729
Short name T1202
Test name
Test status
Simulation time 3475690967 ps
CPU time 9.98 seconds
Started Mar 19 12:28:33 PM PDT 24
Finished Mar 19 12:28:44 PM PDT 24
Peak memory 206420 kb
Host smart-b843d2de-3d96-4759-a170-3b9e298fb821
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032671729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.4032671
729 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.318896502
Short name T1092
Test name
Test status
Simulation time 579309960 ps
CPU time 15.59 seconds
Started Mar 19 12:28:13 PM PDT 24
Finished Mar 19 12:28:29 PM PDT 24
Peak memory 206364 kb
Host smart-c64fdbf5-41f1-4582-890e-c1207d13ab17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318896502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.31889650
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.3214435569
Short name T1107
Test name
Test status
Simulation time 97020519 ps
CPU time 1.04 seconds
Started Mar 19 12:28:24 PM PDT 24
Finished Mar 19 12:28:25 PM PDT 24
Peak memory 206376 kb
Host smart-3e4b08d4-a6ae-4193-9bc2-a3e6eb43e3b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214435569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.3214435
569 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2421460398
Short name T1228
Test name
Test status
Simulation time 46869450 ps
CPU time 1.54 seconds
Started Mar 19 12:28:37 PM PDT 24
Finished Mar 19 12:28:39 PM PDT 24
Peak memory 214636 kb
Host smart-ecd871b2-c815-43ee-ac0e-673815eb6241
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421460398 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.2421460398 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.3850325368
Short name T1192
Test name
Test status
Simulation time 62744720 ps
CPU time 0.92 seconds
Started Mar 19 12:28:16 PM PDT 24
Finished Mar 19 12:28:17 PM PDT 24
Peak memory 206280 kb
Host smart-97d76d19-f119-4599-a964-e48d04fa5ba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850325368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.3850325368 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.2079585840
Short name T1104
Test name
Test status
Simulation time 28946998 ps
CPU time 0.76 seconds
Started Mar 19 12:29:37 PM PDT 24
Finished Mar 19 12:29:37 PM PDT 24
Peak memory 206392 kb
Host smart-4f27ff54-7f3d-4059-96f9-f4e053c5aa0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079585840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2079585840 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.3275660296
Short name T1106
Test name
Test status
Simulation time 34250063 ps
CPU time 0.72 seconds
Started Mar 19 12:29:31 PM PDT 24
Finished Mar 19 12:29:32 PM PDT 24
Peak memory 206340 kb
Host smart-4623d88c-6ec3-4dc2-9394-2509ff0e33c7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275660296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.3275660296
+enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3385765388
Short name T1159
Test name
Test status
Simulation time 427994702 ps
CPU time 2.43 seconds
Started Mar 19 12:28:21 PM PDT 24
Finished Mar 19 12:28:24 PM PDT 24
Peak memory 214764 kb
Host smart-9b47132d-23ad-4f7e-bd2a-69a1d3367c06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385765388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.3385765388 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.11848255
Short name T105
Test name
Test status
Simulation time 51567128 ps
CPU time 1.19 seconds
Started Mar 19 12:28:36 PM PDT 24
Finished Mar 19 12:28:38 PM PDT 24
Peak memory 214908 kb
Host smart-4496c7e0-7273-4edb-a8b7-cf11dd99f446
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11848255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_er
rors.11848255 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3633370179
Short name T1099
Test name
Test status
Simulation time 118954868 ps
CPU time 1.67 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:29:04 PM PDT 24
Peak memory 215140 kb
Host smart-4448b821-91bf-475e-bc02-c1790ff1bbf3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633370179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.3633370179 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.3519272453
Short name T1142
Test name
Test status
Simulation time 113969524 ps
CPU time 1.65 seconds
Started Mar 19 12:28:30 PM PDT 24
Finished Mar 19 12:28:32 PM PDT 24
Peak memory 214692 kb
Host smart-a2f6cbde-56b6-44ed-9fa2-c802389bcc98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519272453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.3519272453 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.1656131084
Short name T1100
Test name
Test status
Simulation time 402157484 ps
CPU time 8.9 seconds
Started Mar 19 12:28:15 PM PDT 24
Finished Mar 19 12:28:24 PM PDT 24
Peak memory 206372 kb
Host smart-a5e93b77-7cd2-4473-b960-9c00f1b374e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656131084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.1656131
084 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.26858002
Short name T1162
Test name
Test status
Simulation time 158200877 ps
CPU time 8.18 seconds
Started Mar 19 12:29:12 PM PDT 24
Finished Mar 19 12:29:22 PM PDT 24
Peak memory 206388 kb
Host smart-2e2c2ad4-c5c0-447b-94b5-ffeed07fa67a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26858002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.26858002
+enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.148812690
Short name T1185
Test name
Test status
Simulation time 121676050 ps
CPU time 0.93 seconds
Started Mar 19 12:29:13 PM PDT 24
Finished Mar 19 12:29:16 PM PDT 24
Peak memory 206268 kb
Host smart-54f8e3f9-d694-49de-b7c2-73cc2b48f05d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148812690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.14881269
0 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3891132319
Short name T1229
Test name
Test status
Simulation time 133075309 ps
CPU time 2.38 seconds
Started Mar 19 12:28:40 PM PDT 24
Finished Mar 19 12:28:43 PM PDT 24
Peak memory 222780 kb
Host smart-2e6e68cb-a5ba-4785-bdbd-55cc3f218fb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891132319 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.3891132319 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.4256452594
Short name T1191
Test name
Test status
Simulation time 41467754 ps
CPU time 0.91 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:29:03 PM PDT 24
Peak memory 206328 kb
Host smart-7de67f1e-9392-4c21-9d8f-97d990f6f779
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256452594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.4256452594 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.1837984328
Short name T1211
Test name
Test status
Simulation time 125637029 ps
CPU time 0.83 seconds
Started Mar 19 12:28:26 PM PDT 24
Finished Mar 19 12:28:27 PM PDT 24
Peak memory 206292 kb
Host smart-92e0b94b-c04b-4304-8033-de633d1277fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837984328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.1837984328 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.1211110106
Short name T139
Test name
Test status
Simulation time 33624288 ps
CPU time 1.17 seconds
Started Mar 19 12:28:11 PM PDT 24
Finished Mar 19 12:28:12 PM PDT 24
Peak memory 214572 kb
Host smart-2497f946-c561-41d4-aee7-20acfd9e7211
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211110106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.1211110106 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3445725917
Short name T1087
Test name
Test status
Simulation time 10065631 ps
CPU time 0.73 seconds
Started Mar 19 12:28:59 PM PDT 24
Finished Mar 19 12:29:00 PM PDT 24
Peak memory 206312 kb
Host smart-b96f12a3-13a6-4ac9-9124-c7b6f6811258
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445725917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.3445725917
+enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2713226715
Short name T1111
Test name
Test status
Simulation time 27562234 ps
CPU time 1.52 seconds
Started Mar 19 12:28:16 PM PDT 24
Finished Mar 19 12:28:18 PM PDT 24
Peak memory 214668 kb
Host smart-4d641413-ad99-4759-85f3-7db70adb5a59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713226715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.2713226715 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.2114482340
Short name T1177
Test name
Test status
Simulation time 177737233 ps
CPU time 1.13 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:28:44 PM PDT 24
Peak memory 215444 kb
Host smart-adcaea2d-b292-4342-aaa9-c3b32192e629
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114482340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.2114482340 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2396048106
Short name T106
Test name
Test status
Simulation time 472467474 ps
CPU time 2.9 seconds
Started Mar 19 12:28:16 PM PDT 24
Finished Mar 19 12:28:19 PM PDT 24
Peak memory 222188 kb
Host smart-d9748dd4-55c9-477c-bcb3-6a45619676b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396048106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.2396048106 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.993610505
Short name T1114
Test name
Test status
Simulation time 47587177 ps
CPU time 1.51 seconds
Started Mar 19 12:28:15 PM PDT 24
Finished Mar 19 12:28:27 PM PDT 24
Peak memory 214668 kb
Host smart-c422ff4e-6ca4-4481-9f97-302d8df1d630
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993610505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.993610505 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.1962488514
Short name T1194
Test name
Test status
Simulation time 399422728 ps
CPU time 2.52 seconds
Started Mar 19 12:28:54 PM PDT 24
Finished Mar 19 12:28:57 PM PDT 24
Peak memory 206380 kb
Host smart-69c5c1f1-de53-41d1-9996-061177580d1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962488514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.19624
88514 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2612165768
Short name T1136
Test name
Test status
Simulation time 78095357 ps
CPU time 1.38 seconds
Started Mar 19 12:28:25 PM PDT 24
Finished Mar 19 12:28:27 PM PDT 24
Peak memory 222780 kb
Host smart-8842f721-0cf4-449c-8e01-6cc88999ef68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612165768 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.2612165768 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1170054942
Short name T1115
Test name
Test status
Simulation time 16299217 ps
CPU time 0.86 seconds
Started Mar 19 12:29:09 PM PDT 24
Finished Mar 19 12:29:10 PM PDT 24
Peak memory 206312 kb
Host smart-cde19578-2c4e-4f18-bf67-389f4db89f4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170054942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1170054942 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.940143141
Short name T1227
Test name
Test status
Simulation time 14315414 ps
CPU time 0.72 seconds
Started Mar 19 12:28:29 PM PDT 24
Finished Mar 19 12:28:30 PM PDT 24
Peak memory 206208 kb
Host smart-9200973b-b2a2-4220-8d3b-cf6aedf05fa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940143141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.940143141 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1638872245
Short name T1236
Test name
Test status
Simulation time 439272921 ps
CPU time 2.27 seconds
Started Mar 19 12:28:18 PM PDT 24
Finished Mar 19 12:28:21 PM PDT 24
Peak memory 214716 kb
Host smart-604b0c03-5f36-4b80-8c48-4b748db27827
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638872245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.1638872245 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1209117892
Short name T109
Test name
Test status
Simulation time 16845078 ps
CPU time 0.83 seconds
Started Mar 19 12:28:15 PM PDT 24
Finished Mar 19 12:28:16 PM PDT 24
Peak memory 206244 kb
Host smart-bc10fe34-ca42-4de6-a885-844cc9f9d49d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209117892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.1209117892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.673014466
Short name T1187
Test name
Test status
Simulation time 249861733 ps
CPU time 1.77 seconds
Started Mar 19 12:28:44 PM PDT 24
Finished Mar 19 12:28:45 PM PDT 24
Peak memory 214880 kb
Host smart-96ca3c2a-1fa0-4776-b48d-d90727b97b94
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673014466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac
_shadow_reg_errors_with_csr_rw.673014466 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.2073021303
Short name T148
Test name
Test status
Simulation time 290117136 ps
CPU time 2.26 seconds
Started Mar 19 12:28:51 PM PDT 24
Finished Mar 19 12:28:54 PM PDT 24
Peak memory 222848 kb
Host smart-fefdc6af-3e88-4c02-88fb-cc1697cd544f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073021303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2073021303 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1034108098
Short name T1208
Test name
Test status
Simulation time 191219485 ps
CPU time 1.57 seconds
Started Mar 19 12:29:17 PM PDT 24
Finished Mar 19 12:29:19 PM PDT 24
Peak memory 222812 kb
Host smart-c325b674-d565-4971-a631-198ef1369d01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034108098 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.1034108098 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2132314066
Short name T1135
Test name
Test status
Simulation time 32116455 ps
CPU time 1.05 seconds
Started Mar 19 12:28:14 PM PDT 24
Finished Mar 19 12:28:16 PM PDT 24
Peak memory 206416 kb
Host smart-4e17b835-8622-4a46-9c86-0e6eeea26f24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132314066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2132314066 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.1326157915
Short name T1199
Test name
Test status
Simulation time 15637844 ps
CPU time 0.77 seconds
Started Mar 19 12:28:34 PM PDT 24
Finished Mar 19 12:28:37 PM PDT 24
Peak memory 206280 kb
Host smart-e623ef85-ee9e-48f2-b377-e56f2bea0d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326157915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1326157915 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3285719831
Short name T1095
Test name
Test status
Simulation time 104416291 ps
CPU time 1.56 seconds
Started Mar 19 12:29:25 PM PDT 24
Finished Mar 19 12:29:27 PM PDT 24
Peak memory 214672 kb
Host smart-f0e6759d-5734-402e-9510-a9da324d280d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285719831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.3285719831 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3513743328
Short name T1138
Test name
Test status
Simulation time 40578120 ps
CPU time 0.98 seconds
Started Mar 19 12:29:37 PM PDT 24
Finished Mar 19 12:29:38 PM PDT 24
Peak memory 206400 kb
Host smart-8aa4776f-fc59-4e07-935f-40c3623f43d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513743328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.3513743328 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.807764344
Short name T1196
Test name
Test status
Simulation time 139579439 ps
CPU time 2.74 seconds
Started Mar 19 12:28:25 PM PDT 24
Finished Mar 19 12:28:28 PM PDT 24
Peak memory 222804 kb
Host smart-60b36425-61dc-4cb0-8e6e-7dadd93a5e2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807764344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac
_shadow_reg_errors_with_csr_rw.807764344 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.3490833555
Short name T1169
Test name
Test status
Simulation time 526627697 ps
CPU time 2.94 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:29:05 PM PDT 24
Peak memory 214696 kb
Host smart-75fcd517-c9b8-4fb7-9c25-d47b1a31a74e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490833555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.3490833555 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3844790217
Short name T1179
Test name
Test status
Simulation time 388709381 ps
CPU time 2.7 seconds
Started Mar 19 12:28:13 PM PDT 24
Finished Mar 19 12:28:16 PM PDT 24
Peak memory 214712 kb
Host smart-871ab2a7-a96c-4c13-9fc0-33256f5ac489
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844790217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3844
790217 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.474702888
Short name T1118
Test name
Test status
Simulation time 276141408 ps
CPU time 1.47 seconds
Started Mar 19 12:28:32 PM PDT 24
Finished Mar 19 12:28:34 PM PDT 24
Peak memory 214652 kb
Host smart-3ba16bd0-67bd-4241-a59d-bc5ce7cae884
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474702888 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.474702888 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.2052657341
Short name T1088
Test name
Test status
Simulation time 18096775 ps
CPU time 0.87 seconds
Started Mar 19 12:28:49 PM PDT 24
Finished Mar 19 12:28:51 PM PDT 24
Peak memory 206284 kb
Host smart-d7abbbe0-aa76-4d4d-b421-e9e628eca884
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052657341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2052657341 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.1966311141
Short name T1174
Test name
Test status
Simulation time 48246777 ps
CPU time 0.79 seconds
Started Mar 19 12:28:45 PM PDT 24
Finished Mar 19 12:28:46 PM PDT 24
Peak memory 206280 kb
Host smart-afffeda1-233a-4105-8a8a-6220cdea815b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966311141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.1966311141 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3493530321
Short name T1086
Test name
Test status
Simulation time 36627767 ps
CPU time 1.91 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:28:44 PM PDT 24
Peak memory 214592 kb
Host smart-567f72ed-d6fd-4ed1-976b-2246d292aa50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493530321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.3493530321 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2050679677
Short name T1198
Test name
Test status
Simulation time 24286414 ps
CPU time 1.15 seconds
Started Mar 19 12:28:49 PM PDT 24
Finished Mar 19 12:28:51 PM PDT 24
Peak memory 215032 kb
Host smart-6eacad81-cedc-4ed5-80cd-7049325b7293
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050679677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.2050679677 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2974845341
Short name T113
Test name
Test status
Simulation time 64685746 ps
CPU time 2.4 seconds
Started Mar 19 12:28:18 PM PDT 24
Finished Mar 19 12:28:21 PM PDT 24
Peak memory 214880 kb
Host smart-4f5e33eb-6023-4704-976f-d2b020b1e7da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974845341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.2974845341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.1706198472
Short name T1102
Test name
Test status
Simulation time 26925051 ps
CPU time 1.49 seconds
Started Mar 19 12:28:46 PM PDT 24
Finished Mar 19 12:28:48 PM PDT 24
Peak memory 214732 kb
Host smart-9b3b5f49-4921-4c70-912b-6af2cadf5397
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706198472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.1706198472 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.132823253
Short name T180
Test name
Test status
Simulation time 109234066 ps
CPU time 3.85 seconds
Started Mar 19 12:28:38 PM PDT 24
Finished Mar 19 12:28:42 PM PDT 24
Peak memory 214584 kb
Host smart-f6672491-da2d-468b-932b-8957a6df0c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132823253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.13282
3253 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.4269081282
Short name T1156
Test name
Test status
Simulation time 603037821 ps
CPU time 2.18 seconds
Started Mar 19 12:28:53 PM PDT 24
Finished Mar 19 12:28:56 PM PDT 24
Peak memory 222776 kb
Host smart-a8410a4b-ea68-45bf-ad9f-165add6a84f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269081282 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.4269081282 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2155533510
Short name T183
Test name
Test status
Simulation time 25702887 ps
CPU time 1.02 seconds
Started Mar 19 12:28:39 PM PDT 24
Finished Mar 19 12:28:40 PM PDT 24
Peak memory 206380 kb
Host smart-ceb2a611-7df2-4a96-85ef-d8f3e85f8307
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155533510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2155533510 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.4134237660
Short name T1119
Test name
Test status
Simulation time 15490707 ps
CPU time 0.77 seconds
Started Mar 19 12:28:37 PM PDT 24
Finished Mar 19 12:28:38 PM PDT 24
Peak memory 206292 kb
Host smart-1382da7c-2138-47d8-97fd-4e0b8d35cc20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134237660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.4134237660 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3508209706
Short name T1125
Test name
Test status
Simulation time 245183727 ps
CPU time 1.56 seconds
Started Mar 19 12:28:36 PM PDT 24
Finished Mar 19 12:28:38 PM PDT 24
Peak memory 214620 kb
Host smart-38be1e2e-5534-4df9-9dd5-3cabd7f24690
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508209706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.3508209706 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2505850000
Short name T1218
Test name
Test status
Simulation time 84062606 ps
CPU time 1.21 seconds
Started Mar 19 12:28:37 PM PDT 24
Finished Mar 19 12:28:44 PM PDT 24
Peak memory 214960 kb
Host smart-9bfae2e6-d47f-459b-afdd-b377d01c34b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505850000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.2505850000 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.2509716614
Short name T1096
Test name
Test status
Simulation time 142024531 ps
CPU time 2.6 seconds
Started Mar 19 12:28:19 PM PDT 24
Finished Mar 19 12:28:22 PM PDT 24
Peak memory 214700 kb
Host smart-40693200-749d-4e32-bfdb-e69aa1814c52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509716614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2509716614 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2435369952
Short name T172
Test name
Test status
Simulation time 819068408 ps
CPU time 4.57 seconds
Started Mar 19 12:29:16 PM PDT 24
Finished Mar 19 12:29:21 PM PDT 24
Peak memory 206340 kb
Host smart-7d31356d-6482-4287-8ea7-e5d0f1c744d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435369952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.2435
369952 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2752375241
Short name T1147
Test name
Test status
Simulation time 168373970 ps
CPU time 1.97 seconds
Started Mar 19 12:28:30 PM PDT 24
Finished Mar 19 12:28:33 PM PDT 24
Peak memory 222848 kb
Host smart-fd0aed49-2f4b-41bd-9654-5b16ad71cffa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752375241 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.2752375241 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1811725960
Short name T1101
Test name
Test status
Simulation time 17517519 ps
CPU time 0.92 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:29:03 PM PDT 24
Peak memory 206328 kb
Host smart-bee12527-19ab-465d-8509-b339f29d324e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811725960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1811725960 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.699957745
Short name T1148
Test name
Test status
Simulation time 21094953 ps
CPU time 0.72 seconds
Started Mar 19 12:28:21 PM PDT 24
Finished Mar 19 12:28:21 PM PDT 24
Peak memory 206284 kb
Host smart-a0b8db86-d4ea-417f-91ef-25f601dcac42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699957745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.699957745 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1652944927
Short name T1232
Test name
Test status
Simulation time 110580232 ps
CPU time 2.35 seconds
Started Mar 19 12:29:05 PM PDT 24
Finished Mar 19 12:29:07 PM PDT 24
Peak memory 214896 kb
Host smart-f0bffaff-0d26-4ef4-8289-66de61797e32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652944927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.1652944927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.775162435
Short name T121
Test name
Test status
Simulation time 14574901 ps
CPU time 0.88 seconds
Started Mar 19 12:28:16 PM PDT 24
Finished Mar 19 12:28:17 PM PDT 24
Peak memory 206352 kb
Host smart-f712d92b-33f3-4630-8600-70044a6d2632
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775162435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_
errors.775162435 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2863875592
Short name T1160
Test name
Test status
Simulation time 124135004 ps
CPU time 2.78 seconds
Started Mar 19 12:28:43 PM PDT 24
Finished Mar 19 12:28:46 PM PDT 24
Peak memory 214924 kb
Host smart-1383025a-ea91-4821-9953-90e8fb5ceab9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863875592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.2863875592 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.3534360922
Short name T1141
Test name
Test status
Simulation time 87240368 ps
CPU time 2.16 seconds
Started Mar 19 12:28:43 PM PDT 24
Finished Mar 19 12:28:46 PM PDT 24
Peak memory 214772 kb
Host smart-088b5aa8-4c2a-4fe4-ab2b-4ce97753ba30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534360922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.3534360922 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.4251450023
Short name T171
Test name
Test status
Simulation time 833272771 ps
CPU time 4.89 seconds
Started Mar 19 12:28:55 PM PDT 24
Finished Mar 19 12:29:00 PM PDT 24
Peak memory 218080 kb
Host smart-4e7bf632-4cb8-4040-9c47-3e3ddb73b03a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251450023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.4251
450023 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.579428751
Short name T125
Test name
Test status
Simulation time 32935033 ps
CPU time 1.67 seconds
Started Mar 19 12:28:47 PM PDT 24
Finished Mar 19 12:28:48 PM PDT 24
Peak memory 222800 kb
Host smart-4b9579bd-87f8-4936-a641-d8a20033e203
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579428751 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.579428751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2574158148
Short name T1171
Test name
Test status
Simulation time 36577808 ps
CPU time 1.09 seconds
Started Mar 19 12:28:31 PM PDT 24
Finished Mar 19 12:28:32 PM PDT 24
Peak memory 206400 kb
Host smart-9a9b0952-8b4a-4815-b880-f721babeffc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574158148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2574158148 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.1424355901
Short name T1123
Test name
Test status
Simulation time 24014635 ps
CPU time 0.79 seconds
Started Mar 19 12:28:51 PM PDT 24
Finished Mar 19 12:28:52 PM PDT 24
Peak memory 206396 kb
Host smart-e8646816-0708-4f74-b0e4-634eafdecdc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424355901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1424355901 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.988643993
Short name T144
Test name
Test status
Simulation time 64718863 ps
CPU time 1.61 seconds
Started Mar 19 12:28:55 PM PDT 24
Finished Mar 19 12:28:57 PM PDT 24
Peak memory 214568 kb
Host smart-b261ce3e-0b68-4b8b-a8aa-7e7d07c25eba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988643993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr
_outstanding.988643993 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1250512213
Short name T1233
Test name
Test status
Simulation time 19524194 ps
CPU time 0.85 seconds
Started Mar 19 12:28:19 PM PDT 24
Finished Mar 19 12:28:20 PM PDT 24
Peak memory 206436 kb
Host smart-3d455e42-8f12-4185-bf6f-2cefd23ecaac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250512213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.1250512213 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.121662816
Short name T100
Test name
Test status
Simulation time 347160031 ps
CPU time 2.58 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:29:37 PM PDT 24
Peak memory 214708 kb
Host smart-2ae4f2ad-ee52-4147-937e-6f8943dfeaf9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121662816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac
_shadow_reg_errors_with_csr_rw.121662816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.2955404531
Short name T1137
Test name
Test status
Simulation time 89096491 ps
CPU time 2.54 seconds
Started Mar 19 12:28:23 PM PDT 24
Finished Mar 19 12:28:26 PM PDT 24
Peak memory 214692 kb
Host smart-fa8b76a4-e016-4976-ac28-c64cf68a4b70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955404531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.2955404531 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3513643253
Short name T169
Test name
Test status
Simulation time 2024336026 ps
CPU time 3.11 seconds
Started Mar 19 12:29:14 PM PDT 24
Finished Mar 19 12:29:20 PM PDT 24
Peak memory 214544 kb
Host smart-69503ed2-19dc-47c9-97d0-d440622da653
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513643253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3513
643253 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2669917334
Short name T1089
Test name
Test status
Simulation time 62003238 ps
CPU time 1.43 seconds
Started Mar 19 12:29:15 PM PDT 24
Finished Mar 19 12:29:18 PM PDT 24
Peak memory 222896 kb
Host smart-87ae2b75-7685-4e79-820b-bc6c67ba0924
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669917334 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.2669917334 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.3293045998
Short name T181
Test name
Test status
Simulation time 51567807 ps
CPU time 1.18 seconds
Started Mar 19 12:29:00 PM PDT 24
Finished Mar 19 12:29:01 PM PDT 24
Peak memory 206420 kb
Host smart-45ef4d75-adf1-49b6-a216-d510e06fddf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293045998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.3293045998 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.1218416757
Short name T1127
Test name
Test status
Simulation time 13872848 ps
CPU time 0.76 seconds
Started Mar 19 12:29:38 PM PDT 24
Finished Mar 19 12:29:39 PM PDT 24
Peak memory 206288 kb
Host smart-919c5b4a-0931-40b7-9196-7b6d69bfe4b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218416757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.1218416757 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.536040728
Short name T1173
Test name
Test status
Simulation time 103648704 ps
CPU time 1.48 seconds
Started Mar 19 12:29:18 PM PDT 24
Finished Mar 19 12:29:20 PM PDT 24
Peak memory 214688 kb
Host smart-21dd67ae-d77a-4014-bb58-5a9482c7290b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536040728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr
_outstanding.536040728 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2799494683
Short name T1161
Test name
Test status
Simulation time 489616439 ps
CPU time 1.26 seconds
Started Mar 19 12:29:03 PM PDT 24
Finished Mar 19 12:29:04 PM PDT 24
Peak memory 214996 kb
Host smart-5809b5e9-3a9e-4789-9306-ca9b19d4f1ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799494683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.2799494683 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.577691950
Short name T1223
Test name
Test status
Simulation time 103031338 ps
CPU time 1.51 seconds
Started Mar 19 12:28:48 PM PDT 24
Finished Mar 19 12:28:51 PM PDT 24
Peak memory 214652 kb
Host smart-2f43b717-6792-44a3-8df3-a7addb3ee3c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577691950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac
_shadow_reg_errors_with_csr_rw.577691950 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.2916078150
Short name T1126
Test name
Test status
Simulation time 99909445 ps
CPU time 1.96 seconds
Started Mar 19 12:28:18 PM PDT 24
Finished Mar 19 12:28:20 PM PDT 24
Peak memory 214672 kb
Host smart-bf1cc605-9f4f-4c9a-b76a-f6a95ea37eba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916078150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2916078150 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.4047071115
Short name T1091
Test name
Test status
Simulation time 33663223 ps
CPU time 2.28 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:28:45 PM PDT 24
Peak memory 222832 kb
Host smart-2987bb32-1ad7-48b4-99ff-1aec5e01b60c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047071115 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.4047071115 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.812566375
Short name T1182
Test name
Test status
Simulation time 35104147 ps
CPU time 0.92 seconds
Started Mar 19 12:29:17 PM PDT 24
Finished Mar 19 12:29:19 PM PDT 24
Peak memory 206288 kb
Host smart-3c568c0a-62cf-45ac-95cd-c52cef292168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812566375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.812566375 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.3989907119
Short name T1145
Test name
Test status
Simulation time 45212491 ps
CPU time 0.75 seconds
Started Mar 19 12:29:22 PM PDT 24
Finished Mar 19 12:29:23 PM PDT 24
Peak memory 206276 kb
Host smart-a979a46d-3f25-42c2-b48b-86a48f651981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989907119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3989907119 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2289695821
Short name T1163
Test name
Test status
Simulation time 120125785 ps
CPU time 2.44 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:28:45 PM PDT 24
Peak memory 214628 kb
Host smart-aaedb6ef-a792-400c-8643-d854acbde988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289695821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.2289695821 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.4032256395
Short name T1225
Test name
Test status
Simulation time 55556014 ps
CPU time 1.21 seconds
Started Mar 19 12:29:03 PM PDT 24
Finished Mar 19 12:29:04 PM PDT 24
Peak memory 215016 kb
Host smart-9c5d934e-c810-4ab5-8cd6-2446b17a4150
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032256395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.4032256395 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3287213470
Short name T1200
Test name
Test status
Simulation time 98820348 ps
CPU time 2.88 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:28:45 PM PDT 24
Peak memory 215036 kb
Host smart-c8c91034-0aa6-4fa9-84ed-2a6d3feb3c22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287213470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.3287213470 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.315640813
Short name T134
Test name
Test status
Simulation time 21070218 ps
CPU time 1.31 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:28:44 PM PDT 24
Peak memory 214544 kb
Host smart-45738ec5-5e5c-46a5-8839-291529b9fdc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315640813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.315640813 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3373389834
Short name T167
Test name
Test status
Simulation time 63725327 ps
CPU time 2.35 seconds
Started Mar 19 12:28:52 PM PDT 24
Finished Mar 19 12:28:54 PM PDT 24
Peak memory 214576 kb
Host smart-dff8cf74-ac30-4303-9dfd-3f1f60855c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373389834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3373
389834 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1891395277
Short name T1172
Test name
Test status
Simulation time 196117449 ps
CPU time 1.53 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:28:44 PM PDT 24
Peak memory 214604 kb
Host smart-882bc0b2-0566-408d-a424-1db407739dbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891395277 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.1891395277 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.3300000863
Short name T1113
Test name
Test status
Simulation time 63094473 ps
CPU time 1.04 seconds
Started Mar 19 12:28:30 PM PDT 24
Finished Mar 19 12:28:31 PM PDT 24
Peak memory 206368 kb
Host smart-525da8eb-71d6-4d9c-9cd3-2cfa8e9a7b62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300000863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.3300000863 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.2058997068
Short name T1189
Test name
Test status
Simulation time 48737676 ps
CPU time 0.8 seconds
Started Mar 19 12:28:43 PM PDT 24
Finished Mar 19 12:28:48 PM PDT 24
Peak memory 206284 kb
Host smart-dd7c5176-81f6-4e25-95f6-0c5ce0344c8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058997068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.2058997068 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2543504591
Short name T1221
Test name
Test status
Simulation time 32717238 ps
CPU time 1.57 seconds
Started Mar 19 12:29:20 PM PDT 24
Finished Mar 19 12:29:22 PM PDT 24
Peak memory 214860 kb
Host smart-cc692a01-0420-44e1-aa3e-f8c7042a40f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543504591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.2543504591 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3765708085
Short name T1183
Test name
Test status
Simulation time 74887735 ps
CPU time 1.93 seconds
Started Mar 19 12:28:43 PM PDT 24
Finished Mar 19 12:28:45 PM PDT 24
Peak memory 222736 kb
Host smart-2f95feaa-bffd-4e24-804a-acc8aa3a5d9b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765708085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.3765708085 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.3808240275
Short name T1094
Test name
Test status
Simulation time 224843601 ps
CPU time 1.68 seconds
Started Mar 19 12:28:17 PM PDT 24
Finished Mar 19 12:28:19 PM PDT 24
Peak memory 214744 kb
Host smart-ff440996-e651-466d-b01f-8f9d949d837d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808240275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.3808240275 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3912640537
Short name T1205
Test name
Test status
Simulation time 75956710 ps
CPU time 2.58 seconds
Started Mar 19 12:28:48 PM PDT 24
Finished Mar 19 12:28:51 PM PDT 24
Peak memory 222804 kb
Host smart-2c4e0c39-6883-441b-b655-35eb9b1b58dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912640537 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.3912640537 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3095751696
Short name T1134
Test name
Test status
Simulation time 125880430 ps
CPU time 1.15 seconds
Started Mar 19 12:29:12 PM PDT 24
Finished Mar 19 12:29:15 PM PDT 24
Peak memory 206408 kb
Host smart-4120e2cc-681f-4f9d-94f6-cc7d06f9c503
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095751696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.3095751696 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.3507453146
Short name T1197
Test name
Test status
Simulation time 12801867 ps
CPU time 0.75 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:29:03 PM PDT 24
Peak memory 206288 kb
Host smart-ad6887b3-b8ce-45de-964d-adab5de94a65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507453146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.3507453146 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.98414612
Short name T145
Test name
Test status
Simulation time 247564139 ps
CPU time 1.63 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:28:44 PM PDT 24
Peak memory 214508 kb
Host smart-2e8b18a3-3d91-47a9-8fc0-8b8212a7fa93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98414612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_
outstanding.98414612 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1837643676
Short name T104
Test name
Test status
Simulation time 51712751 ps
CPU time 1.25 seconds
Started Mar 19 12:28:45 PM PDT 24
Finished Mar 19 12:28:46 PM PDT 24
Peak memory 215068 kb
Host smart-d1dbf553-38de-4fca-bf4e-31f875256836
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837643676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.1837643676 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.4101632167
Short name T103
Test name
Test status
Simulation time 139027694 ps
CPU time 3.38 seconds
Started Mar 19 12:28:32 PM PDT 24
Finished Mar 19 12:28:35 PM PDT 24
Peak memory 223080 kb
Host smart-7e9071b2-4d27-4749-b633-e6d88539fa80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101632167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.4101632167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2193076016
Short name T1097
Test name
Test status
Simulation time 302840511 ps
CPU time 1.98 seconds
Started Mar 19 12:28:16 PM PDT 24
Finished Mar 19 12:28:18 PM PDT 24
Peak memory 214704 kb
Host smart-f0441ff0-3e85-4c33-afe8-1dbe9f693a2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193076016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.2193076016 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.4059205617
Short name T175
Test name
Test status
Simulation time 1008185862 ps
CPU time 4.86 seconds
Started Mar 19 12:29:01 PM PDT 24
Finished Mar 19 12:29:07 PM PDT 24
Peak memory 214576 kb
Host smart-1f2ca3cc-1d4f-4d43-b3e3-aed2e30da649
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059205617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.4059
205617 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2900130381
Short name T1226
Test name
Test status
Simulation time 1009643265 ps
CPU time 10.09 seconds
Started Mar 19 12:28:28 PM PDT 24
Finished Mar 19 12:28:38 PM PDT 24
Peak memory 206380 kb
Host smart-332445e2-2674-4247-9060-978f1c8da89a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900130381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.2900130
381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3213319036
Short name T143
Test name
Test status
Simulation time 1487384236 ps
CPU time 19.88 seconds
Started Mar 19 12:28:12 PM PDT 24
Finished Mar 19 12:28:32 PM PDT 24
Peak memory 206364 kb
Host smart-ae68d17a-2ebc-4388-8d7b-caf0f0eadc93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213319036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.3213319
036 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1758620502
Short name T1217
Test name
Test status
Simulation time 26102718 ps
CPU time 1.08 seconds
Started Mar 19 12:28:22 PM PDT 24
Finished Mar 19 12:28:23 PM PDT 24
Peak memory 206348 kb
Host smart-5313afbf-9873-4dcc-8449-17dbe324243b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758620502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.1758620
502 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.1825938653
Short name T1098
Test name
Test status
Simulation time 345581005 ps
CPU time 1.68 seconds
Started Mar 19 12:29:21 PM PDT 24
Finished Mar 19 12:29:23 PM PDT 24
Peak memory 214620 kb
Host smart-cfbf67a0-0f98-4bc4-9e39-45ca87d5fbc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825938653 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.1825938653 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.2629524580
Short name T1116
Test name
Test status
Simulation time 50707986 ps
CPU time 0.87 seconds
Started Mar 19 12:29:22 PM PDT 24
Finished Mar 19 12:29:23 PM PDT 24
Peak memory 206348 kb
Host smart-ab4eef1f-7fe6-4ce9-82e8-aef1692cb7b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629524580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.2629524580 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.52829164
Short name T1190
Test name
Test status
Simulation time 24494315 ps
CPU time 0.73 seconds
Started Mar 19 12:28:10 PM PDT 24
Finished Mar 19 12:28:11 PM PDT 24
Peak memory 206276 kb
Host smart-639b8961-02d3-4483-8109-7a8b5300a52c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52829164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.52829164 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.2342066199
Short name T138
Test name
Test status
Simulation time 56062776 ps
CPU time 1.13 seconds
Started Mar 19 12:28:40 PM PDT 24
Finished Mar 19 12:28:42 PM PDT 24
Peak memory 214552 kb
Host smart-48b901a0-709d-4105-9f5b-ec4a74adc9e7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342066199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.2342066199 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.3713539322
Short name T1085
Test name
Test status
Simulation time 10333520 ps
CPU time 0.72 seconds
Started Mar 19 12:29:12 PM PDT 24
Finished Mar 19 12:29:14 PM PDT 24
Peak memory 206344 kb
Host smart-75455045-5ccd-47bb-ada5-9eace0e55147
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713539322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.3713539322
+enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.4242469660
Short name T1139
Test name
Test status
Simulation time 161332460 ps
CPU time 2.69 seconds
Started Mar 19 12:28:25 PM PDT 24
Finished Mar 19 12:28:28 PM PDT 24
Peak memory 214580 kb
Host smart-c9ae77e9-e772-45f9-b5f3-dc7ad59d5b5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242469660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.4242469660 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3994353007
Short name T102
Test name
Test status
Simulation time 112558463 ps
CPU time 1.43 seconds
Started Mar 19 12:28:54 PM PDT 24
Finished Mar 19 12:28:56 PM PDT 24
Peak memory 214928 kb
Host smart-bbf9f3ce-0dc6-4c82-8d2b-40a8df779e11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994353007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.3994353007 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2806454455
Short name T1150
Test name
Test status
Simulation time 68764560 ps
CPU time 1.89 seconds
Started Mar 19 12:28:16 PM PDT 24
Finished Mar 19 12:28:18 PM PDT 24
Peak memory 214900 kb
Host smart-08aba7bd-8232-4f63-8dcf-684569259713
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806454455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.2806454455 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.101771824
Short name T124
Test name
Test status
Simulation time 329459503 ps
CPU time 2.35 seconds
Started Mar 19 12:28:15 PM PDT 24
Finished Mar 19 12:28:18 PM PDT 24
Peak memory 222852 kb
Host smart-547a42ed-3357-4b46-b981-94c47ab35adb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101771824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.101771824 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.239756158
Short name T1122
Test name
Test status
Simulation time 198063847 ps
CPU time 2.19 seconds
Started Mar 19 12:29:38 PM PDT 24
Finished Mar 19 12:29:40 PM PDT 24
Peak memory 214648 kb
Host smart-17fa8217-6262-4481-ba6f-9783bec21c35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239756158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.239756
158 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.824587894
Short name T1157
Test name
Test status
Simulation time 13364805 ps
CPU time 0.8 seconds
Started Mar 19 12:28:45 PM PDT 24
Finished Mar 19 12:28:46 PM PDT 24
Peak memory 206420 kb
Host smart-37735431-b92c-4b67-9019-dee54f2407bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824587894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.824587894 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.1278624617
Short name T1220
Test name
Test status
Simulation time 14209858 ps
CPU time 0.76 seconds
Started Mar 19 12:28:57 PM PDT 24
Finished Mar 19 12:28:59 PM PDT 24
Peak memory 206232 kb
Host smart-521e7a90-5302-4e52-88a3-cf24ccb9f824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278624617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1278624617 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.2975405648
Short name T117
Test name
Test status
Simulation time 18358442 ps
CPU time 0.8 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:28:43 PM PDT 24
Peak memory 206296 kb
Host smart-c3ae7d18-7aef-4ab2-821a-1976bf2f6f88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975405648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2975405648 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.2348011697
Short name T1153
Test name
Test status
Simulation time 17359793 ps
CPU time 0.76 seconds
Started Mar 19 12:28:52 PM PDT 24
Finished Mar 19 12:28:53 PM PDT 24
Peak memory 206196 kb
Host smart-7bb80146-ed56-4456-acad-6535d2b5de84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348011697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2348011697 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.2400733257
Short name T1214
Test name
Test status
Simulation time 27894645 ps
CPU time 0.8 seconds
Started Mar 19 12:29:07 PM PDT 24
Finished Mar 19 12:29:08 PM PDT 24
Peak memory 206280 kb
Host smart-7fbee48f-4834-41b5-99d5-dc2652405a4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400733257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2400733257 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.1079133428
Short name T164
Test name
Test status
Simulation time 32125959 ps
CPU time 0.77 seconds
Started Mar 19 12:28:43 PM PDT 24
Finished Mar 19 12:28:43 PM PDT 24
Peak memory 206296 kb
Host smart-31ced99e-f012-48f7-bcf8-380b5d276305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079133428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.1079133428 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.1293532221
Short name T1167
Test name
Test status
Simulation time 11895580 ps
CPU time 0.73 seconds
Started Mar 19 12:28:44 PM PDT 24
Finished Mar 19 12:28:45 PM PDT 24
Peak memory 206252 kb
Host smart-8cf91a45-b4d2-4e25-9c51-89e83ad8c4e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293532221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.1293532221 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.2588817924
Short name T161
Test name
Test status
Simulation time 13840172 ps
CPU time 0.74 seconds
Started Mar 19 12:28:45 PM PDT 24
Finished Mar 19 12:28:46 PM PDT 24
Peak memory 206280 kb
Host smart-499d18ef-8a93-4468-a3b2-19cd3fec702f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588817924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2588817924 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.3817032806
Short name T1213
Test name
Test status
Simulation time 15112192 ps
CPU time 0.77 seconds
Started Mar 19 12:28:28 PM PDT 24
Finished Mar 19 12:28:29 PM PDT 24
Peak memory 206280 kb
Host smart-d0f39bb8-e78c-45b3-b23b-6af5f48e305a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817032806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.3817032806 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.4185753680
Short name T142
Test name
Test status
Simulation time 271253808 ps
CPU time 5.39 seconds
Started Mar 19 12:28:15 PM PDT 24
Finished Mar 19 12:28:20 PM PDT 24
Peak memory 206388 kb
Host smart-f37211e9-fc4f-45fb-8058-2cda53369a27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185753680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.4185753
680 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.3422944206
Short name T146
Test name
Test status
Simulation time 1262063352 ps
CPU time 18.85 seconds
Started Mar 19 12:28:16 PM PDT 24
Finished Mar 19 12:28:36 PM PDT 24
Peak memory 206368 kb
Host smart-f46a2020-0e1e-43ae-a122-a43d76081a00
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422944206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.3422944
206 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.826340897
Short name T1146
Test name
Test status
Simulation time 45331974 ps
CPU time 0.91 seconds
Started Mar 19 12:28:10 PM PDT 24
Finished Mar 19 12:28:12 PM PDT 24
Peak memory 206280 kb
Host smart-000b4b34-aea6-4751-9713-641e459e2b86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826340897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.82634089
7 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1828851889
Short name T126
Test name
Test status
Simulation time 86581001 ps
CPU time 1.47 seconds
Started Mar 19 12:28:47 PM PDT 24
Finished Mar 19 12:28:49 PM PDT 24
Peak memory 214612 kb
Host smart-5999e2b1-a741-40fb-9882-bd093cceb7bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828851889 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.1828851889 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.3649120502
Short name T1120
Test name
Test status
Simulation time 47593871 ps
CPU time 1.11 seconds
Started Mar 19 12:28:37 PM PDT 24
Finished Mar 19 12:28:38 PM PDT 24
Peak memory 206380 kb
Host smart-b5c7a36c-4388-4cf8-99ac-e3a30cb50850
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649120502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.3649120502 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.4007042522
Short name T1234
Test name
Test status
Simulation time 15892212 ps
CPU time 0.75 seconds
Started Mar 19 12:28:38 PM PDT 24
Finished Mar 19 12:28:39 PM PDT 24
Peak memory 206280 kb
Host smart-85eca498-ec96-462b-bc6a-61fa63036183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007042522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.4007042522 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1856549564
Short name T137
Test name
Test status
Simulation time 44186146 ps
CPU time 1.45 seconds
Started Mar 19 12:28:31 PM PDT 24
Finished Mar 19 12:28:33 PM PDT 24
Peak memory 215052 kb
Host smart-ff3852ac-3212-4a16-8e2f-8f3f41555c3f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856549564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.1856549564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.2073565828
Short name T1112
Test name
Test status
Simulation time 74371270 ps
CPU time 0.71 seconds
Started Mar 19 12:28:36 PM PDT 24
Finished Mar 19 12:28:37 PM PDT 24
Peak memory 206320 kb
Host smart-a3e06195-996d-4445-8d09-efb76a8cf630
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073565828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.2073565828
+enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3967343782
Short name T1164
Test name
Test status
Simulation time 365228033 ps
CPU time 1.78 seconds
Started Mar 19 12:28:02 PM PDT 24
Finished Mar 19 12:28:04 PM PDT 24
Peak memory 214568 kb
Host smart-2fb8f8ed-11b9-4578-9ddd-edb98668ddc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967343782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.3967343782 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.1860338184
Short name T1140
Test name
Test status
Simulation time 49569737 ps
CPU time 1.39 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:28:44 PM PDT 24
Peak memory 214928 kb
Host smart-403ef954-f6b8-4e49-abc3-8bf711089e05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860338184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.1860338184 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1961414804
Short name T1143
Test name
Test status
Simulation time 375633897 ps
CPU time 2.77 seconds
Started Mar 19 12:28:18 PM PDT 24
Finished Mar 19 12:28:20 PM PDT 24
Peak memory 223136 kb
Host smart-32067f05-c035-4101-ac0c-2683bdf49500
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961414804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.1961414804 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.337792107
Short name T1131
Test name
Test status
Simulation time 121452819 ps
CPU time 1.99 seconds
Started Mar 19 12:28:06 PM PDT 24
Finished Mar 19 12:28:08 PM PDT 24
Peak memory 214696 kb
Host smart-f42411c9-70ce-4119-81bf-4eb0abad559b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337792107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.337792107 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2912776368
Short name T170
Test name
Test status
Simulation time 105866678 ps
CPU time 2.75 seconds
Started Mar 19 12:28:12 PM PDT 24
Finished Mar 19 12:28:15 PM PDT 24
Peak memory 214616 kb
Host smart-d468bacb-8fd7-4b38-9e21-d48378f79e1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912776368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.29127
76368 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.2534378568
Short name T1219
Test name
Test status
Simulation time 38744491 ps
CPU time 0.73 seconds
Started Mar 19 12:28:44 PM PDT 24
Finished Mar 19 12:28:45 PM PDT 24
Peak memory 206288 kb
Host smart-fff0234b-f077-4750-9c66-c3e13470a3e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534378568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2534378568 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.2151179919
Short name T166
Test name
Test status
Simulation time 52312563 ps
CPU time 0.8 seconds
Started Mar 19 12:28:35 PM PDT 24
Finished Mar 19 12:28:37 PM PDT 24
Peak memory 206292 kb
Host smart-f3bf420f-c007-41c1-a031-0aea42c2ac14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151179919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.2151179919 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.3041980071
Short name T1204
Test name
Test status
Simulation time 19662875 ps
CPU time 0.78 seconds
Started Mar 19 12:29:19 PM PDT 24
Finished Mar 19 12:29:20 PM PDT 24
Peak memory 206296 kb
Host smart-0b8eab79-3371-43ac-8b7a-86d27b631a16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041980071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.3041980071 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.2568026014
Short name T165
Test name
Test status
Simulation time 21292162 ps
CPU time 0.75 seconds
Started Mar 19 12:28:45 PM PDT 24
Finished Mar 19 12:28:46 PM PDT 24
Peak memory 206284 kb
Host smart-75eea178-393f-46cc-bd4f-fcd952c91169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568026014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2568026014 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.3796256147
Short name T147
Test name
Test status
Simulation time 23500942 ps
CPU time 0.76 seconds
Started Mar 19 12:29:14 PM PDT 24
Finished Mar 19 12:29:16 PM PDT 24
Peak memory 206296 kb
Host smart-06dc1d17-3aab-48e9-b0a1-91938ef2cc5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796256147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3796256147 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.3252937489
Short name T1166
Test name
Test status
Simulation time 24059447 ps
CPU time 0.75 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:28:43 PM PDT 24
Peak memory 206260 kb
Host smart-fcfaab06-38dd-43db-ba78-2760434950ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252937489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3252937489 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.3474775548
Short name T1155
Test name
Test status
Simulation time 22007354 ps
CPU time 0.72 seconds
Started Mar 19 12:28:44 PM PDT 24
Finished Mar 19 12:28:46 PM PDT 24
Peak memory 206252 kb
Host smart-b5786b40-de7b-4f5a-87a2-132f8dfc6ea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474775548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.3474775548 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.2951302242
Short name T119
Test name
Test status
Simulation time 19891375 ps
CPU time 0.73 seconds
Started Mar 19 12:28:43 PM PDT 24
Finished Mar 19 12:28:44 PM PDT 24
Peak memory 206280 kb
Host smart-b5853707-5ff1-49e8-8008-401eac57cc33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951302242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2951302242 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.2613084968
Short name T1188
Test name
Test status
Simulation time 13756997 ps
CPU time 0.76 seconds
Started Mar 19 12:28:53 PM PDT 24
Finished Mar 19 12:28:54 PM PDT 24
Peak memory 206316 kb
Host smart-a1067d09-1703-494a-9b7c-0a7bfc95967e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613084968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2613084968 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.3518212053
Short name T1210
Test name
Test status
Simulation time 20012719 ps
CPU time 0.71 seconds
Started Mar 19 12:28:38 PM PDT 24
Finished Mar 19 12:28:39 PM PDT 24
Peak memory 206272 kb
Host smart-236aef02-65e8-4497-be59-489150cfa6c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518212053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3518212053 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2541725460
Short name T1238
Test name
Test status
Simulation time 204192822 ps
CPU time 4.92 seconds
Started Mar 19 12:28:26 PM PDT 24
Finished Mar 19 12:28:31 PM PDT 24
Peak memory 206520 kb
Host smart-98280df2-1a29-4c15-b334-a1da2a1fb9fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541725460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.2541725
460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1487849060
Short name T1109
Test name
Test status
Simulation time 1257708187 ps
CPU time 9.72 seconds
Started Mar 19 12:28:31 PM PDT 24
Finished Mar 19 12:28:41 PM PDT 24
Peak memory 206376 kb
Host smart-da986fd1-5373-402d-bf05-1e530713804b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487849060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.1487849
060 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.791464074
Short name T1093
Test name
Test status
Simulation time 51207888 ps
CPU time 0.9 seconds
Started Mar 19 12:28:43 PM PDT 24
Finished Mar 19 12:28:44 PM PDT 24
Peak memory 206212 kb
Host smart-85990e21-cd85-413d-8509-427b85e40d0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791464074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.79146407
4 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.13862968
Short name T1132
Test name
Test status
Simulation time 91281364 ps
CPU time 1.65 seconds
Started Mar 19 12:28:41 PM PDT 24
Finished Mar 19 12:28:43 PM PDT 24
Peak memory 222760 kb
Host smart-0e595843-637e-4e41-8a29-61cb5b0ef5d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13862968 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.13862968 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.1376583843
Short name T182
Test name
Test status
Simulation time 28213871 ps
CPU time 1.16 seconds
Started Mar 19 12:28:37 PM PDT 24
Finished Mar 19 12:28:38 PM PDT 24
Peak memory 206396 kb
Host smart-acda8a26-93bf-474a-8f48-cfaf723a6df6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376583843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.1376583843 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3983121086
Short name T140
Test name
Test status
Simulation time 42522486 ps
CPU time 1.46 seconds
Started Mar 19 12:28:31 PM PDT 24
Finished Mar 19 12:28:33 PM PDT 24
Peak memory 214720 kb
Host smart-3e1fc102-95d0-4228-a411-8fd0c3285376
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983121086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.3983121086 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.631959592
Short name T1235
Test name
Test status
Simulation time 47380336 ps
CPU time 0.7 seconds
Started Mar 19 12:28:31 PM PDT 24
Finished Mar 19 12:28:32 PM PDT 24
Peak memory 206448 kb
Host smart-0cf93ad8-d396-42d1-8371-a84341aacd79
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631959592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.631959592 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.295158193
Short name T1165
Test name
Test status
Simulation time 136462020 ps
CPU time 1.7 seconds
Started Mar 19 12:28:35 PM PDT 24
Finished Mar 19 12:28:38 PM PDT 24
Peak memory 214560 kb
Host smart-26654b30-e6ae-415f-beb2-9c952f2e35e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295158193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_
outstanding.295158193 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.11319784
Short name T97
Test name
Test status
Simulation time 33074864 ps
CPU time 1.17 seconds
Started Mar 19 12:28:19 PM PDT 24
Finished Mar 19 12:28:21 PM PDT 24
Peak memory 214844 kb
Host smart-e0a3db95-4949-456f-9737-0e2c534a7f1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11319784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_er
rors.11319784 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.204516044
Short name T1129
Test name
Test status
Simulation time 133191728 ps
CPU time 1.74 seconds
Started Mar 19 12:29:39 PM PDT 24
Finished Mar 19 12:29:41 PM PDT 24
Peak memory 214660 kb
Host smart-7a1205a9-1c8e-4ad3-96ee-fab1fa23fdf5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204516044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_
shadow_reg_errors_with_csr_rw.204516044 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.1090614057
Short name T1215
Test name
Test status
Simulation time 93532583 ps
CPU time 1.62 seconds
Started Mar 19 12:28:37 PM PDT 24
Finished Mar 19 12:28:39 PM PDT 24
Peak memory 214808 kb
Host smart-30295370-ee39-497c-84b8-d7fd73eb3bef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090614057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.1090614057 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1444019852
Short name T116
Test name
Test status
Simulation time 309412701 ps
CPU time 3.92 seconds
Started Mar 19 12:28:38 PM PDT 24
Finished Mar 19 12:28:43 PM PDT 24
Peak memory 206472 kb
Host smart-18030681-3323-4717-9a31-396d1a6ef0c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444019852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.14440
19852 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.793516655
Short name T1237
Test name
Test status
Simulation time 22329345 ps
CPU time 0.73 seconds
Started Mar 19 12:28:44 PM PDT 24
Finished Mar 19 12:28:46 PM PDT 24
Peak memory 206308 kb
Host smart-ef2f0a03-549f-4f82-b7d9-799e3e2442c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793516655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.793516655 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.2110208759
Short name T1230
Test name
Test status
Simulation time 13512058 ps
CPU time 0.75 seconds
Started Mar 19 12:28:58 PM PDT 24
Finished Mar 19 12:29:00 PM PDT 24
Peak memory 206296 kb
Host smart-def6e593-1e62-4f1c-b30a-8179f01add5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110208759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.2110208759 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.1774615215
Short name T1154
Test name
Test status
Simulation time 11223347 ps
CPU time 0.72 seconds
Started Mar 19 12:28:46 PM PDT 24
Finished Mar 19 12:28:47 PM PDT 24
Peak memory 206392 kb
Host smart-963a8bf7-e7d6-4772-ae01-538a9f9018a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774615215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1774615215 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.2471476682
Short name T1193
Test name
Test status
Simulation time 60528168 ps
CPU time 0.74 seconds
Started Mar 19 12:28:50 PM PDT 24
Finished Mar 19 12:28:52 PM PDT 24
Peak memory 206280 kb
Host smart-342b2086-90d3-4f16-8d7b-5e9e3ba345df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471476682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.2471476682 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.496872363
Short name T1152
Test name
Test status
Simulation time 21409378 ps
CPU time 0.8 seconds
Started Mar 19 12:28:39 PM PDT 24
Finished Mar 19 12:28:41 PM PDT 24
Peak memory 206296 kb
Host smart-667514c4-ee02-491f-b0c0-8a7e48dca07e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496872363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.496872363 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.2429992776
Short name T163
Test name
Test status
Simulation time 102910996 ps
CPU time 0.77 seconds
Started Mar 19 12:28:58 PM PDT 24
Finished Mar 19 12:28:59 PM PDT 24
Peak memory 206296 kb
Host smart-0c0665d2-b6af-41cf-8cc0-a50af8cc9c0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429992776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2429992776 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.2474352808
Short name T159
Test name
Test status
Simulation time 15683687 ps
CPU time 0.78 seconds
Started Mar 19 12:29:08 PM PDT 24
Finished Mar 19 12:29:10 PM PDT 24
Peak memory 206296 kb
Host smart-2cd0e514-6ae7-44b0-a688-b06575309c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474352808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2474352808 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.900557866
Short name T1178
Test name
Test status
Simulation time 46898016 ps
CPU time 0.72 seconds
Started Mar 19 12:28:54 PM PDT 24
Finished Mar 19 12:28:55 PM PDT 24
Peak memory 206312 kb
Host smart-452d8fd9-b382-4b50-b70f-d83598019b36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900557866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.900557866 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.2476611961
Short name T1195
Test name
Test status
Simulation time 45549236 ps
CPU time 0.79 seconds
Started Mar 19 12:28:36 PM PDT 24
Finished Mar 19 12:28:37 PM PDT 24
Peak memory 206264 kb
Host smart-3f4b8244-08de-4bac-956e-851dcf08bcaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476611961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2476611961 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.3657401234
Short name T1144
Test name
Test status
Simulation time 27803284 ps
CPU time 0.75 seconds
Started Mar 19 12:28:51 PM PDT 24
Finished Mar 19 12:28:52 PM PDT 24
Peak memory 206312 kb
Host smart-dba20c77-1aeb-439b-98f3-e134adfb65da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657401234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3657401234 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.555251209
Short name T1216
Test name
Test status
Simulation time 50538093 ps
CPU time 1.73 seconds
Started Mar 19 12:28:15 PM PDT 24
Finished Mar 19 12:28:17 PM PDT 24
Peak memory 222776 kb
Host smart-dbd7a0ed-b4f2-4b32-9702-f0f7b365591b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555251209 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.555251209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.1913945012
Short name T1105
Test name
Test status
Simulation time 19033084 ps
CPU time 0.92 seconds
Started Mar 19 12:28:40 PM PDT 24
Finished Mar 19 12:28:42 PM PDT 24
Peak memory 206308 kb
Host smart-fc9e6eee-86d6-4d67-ad07-af752c290ab0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913945012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1913945012 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.688500511
Short name T1168
Test name
Test status
Simulation time 60477050 ps
CPU time 0.75 seconds
Started Mar 19 12:28:12 PM PDT 24
Finished Mar 19 12:28:13 PM PDT 24
Peak memory 206256 kb
Host smart-b727de7f-e8eb-4c0f-9293-fc4a2a5c4105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688500511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.688500511 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2194592083
Short name T1181
Test name
Test status
Simulation time 49581921 ps
CPU time 1.55 seconds
Started Mar 19 12:28:38 PM PDT 24
Finished Mar 19 12:28:55 PM PDT 24
Peak memory 214728 kb
Host smart-9343b660-78e5-4c36-8cf2-1b8ab7082f45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194592083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.2194592083 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1439510859
Short name T1224
Test name
Test status
Simulation time 73802726 ps
CPU time 1.04 seconds
Started Mar 19 12:28:27 PM PDT 24
Finished Mar 19 12:28:28 PM PDT 24
Peak memory 206692 kb
Host smart-9b29cbbd-2901-4a47-81b1-bc8dbd83cafd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439510859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.1439510859 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.722749185
Short name T1186
Test name
Test status
Simulation time 26994775 ps
CPU time 1.56 seconds
Started Mar 19 12:28:35 PM PDT 24
Finished Mar 19 12:28:37 PM PDT 24
Peak memory 214928 kb
Host smart-4f8ae643-e1d3-4e66-bfb3-25f3e0a3612a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722749185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_
shadow_reg_errors_with_csr_rw.722749185 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3034408531
Short name T1090
Test name
Test status
Simulation time 158633380 ps
CPU time 2.5 seconds
Started Mar 19 12:28:15 PM PDT 24
Finished Mar 19 12:28:18 PM PDT 24
Peak memory 214672 kb
Host smart-94901326-f8a9-48aa-8bdb-aae4a02eecce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034408531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3034408531 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2241963851
Short name T1184
Test name
Test status
Simulation time 276885544 ps
CPU time 2.54 seconds
Started Mar 19 12:28:43 PM PDT 24
Finished Mar 19 12:28:46 PM PDT 24
Peak memory 214456 kb
Host smart-78052e3c-f3b8-4a77-93f2-ceb15f7b9bbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241963851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.22419
63851 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3733192212
Short name T1124
Test name
Test status
Simulation time 69470644 ps
CPU time 2.15 seconds
Started Mar 19 12:28:23 PM PDT 24
Finished Mar 19 12:28:25 PM PDT 24
Peak memory 222804 kb
Host smart-312e8bba-5143-4dec-8284-771800d58b38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733192212 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.3733192212 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.801916633
Short name T1175
Test name
Test status
Simulation time 37245811 ps
CPU time 1.17 seconds
Started Mar 19 12:28:14 PM PDT 24
Finished Mar 19 12:28:16 PM PDT 24
Peak memory 206448 kb
Host smart-dab215fe-c029-42de-91f8-48c94c38d197
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801916633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.801916633 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.113887225
Short name T160
Test name
Test status
Simulation time 46573832 ps
CPU time 0.73 seconds
Started Mar 19 12:28:16 PM PDT 24
Finished Mar 19 12:28:17 PM PDT 24
Peak memory 206308 kb
Host smart-b224d8e4-8d35-4e48-b976-f664bb4a1102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113887225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.113887225 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3098985896
Short name T1117
Test name
Test status
Simulation time 105844128 ps
CPU time 2.23 seconds
Started Mar 19 12:29:19 PM PDT 24
Finished Mar 19 12:29:21 PM PDT 24
Peak memory 214640 kb
Host smart-92dbee5e-ff7d-4882-adc1-2496a67316a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098985896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.3098985896 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3989393631
Short name T1222
Test name
Test status
Simulation time 53815777 ps
CPU time 1.25 seconds
Started Mar 19 12:28:38 PM PDT 24
Finished Mar 19 12:28:40 PM PDT 24
Peak memory 214916 kb
Host smart-b0d14a88-d638-4ff2-abbb-2f922b32de80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989393631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.3989393631 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1086273599
Short name T108
Test name
Test status
Simulation time 56236798 ps
CPU time 2.29 seconds
Started Mar 19 12:28:13 PM PDT 24
Finished Mar 19 12:28:16 PM PDT 24
Peak memory 214908 kb
Host smart-42022d71-663c-491f-ac32-8f965c68be9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086273599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.1086273599 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.3684443093
Short name T1212
Test name
Test status
Simulation time 46750812 ps
CPU time 1.51 seconds
Started Mar 19 12:28:40 PM PDT 24
Finished Mar 19 12:28:42 PM PDT 24
Peak memory 214804 kb
Host smart-e0a892e1-ce54-4bb2-a393-e300e48d326b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684443093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3684443093 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3518188689
Short name T168
Test name
Test status
Simulation time 562870237 ps
CPU time 4.74 seconds
Started Mar 19 12:28:13 PM PDT 24
Finished Mar 19 12:28:18 PM PDT 24
Peak memory 206396 kb
Host smart-76833f6a-3eba-406b-82a7-1394f705e35f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518188689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.35181
88689 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.58418877
Short name T127
Test name
Test status
Simulation time 82663172 ps
CPU time 1.53 seconds
Started Mar 19 12:28:48 PM PDT 24
Finished Mar 19 12:28:49 PM PDT 24
Peak memory 214644 kb
Host smart-a3bc9de3-1f62-470f-9def-44f59f76963c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58418877 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.58418877 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2294173580
Short name T1121
Test name
Test status
Simulation time 52555264 ps
CPU time 0.99 seconds
Started Mar 19 12:28:18 PM PDT 24
Finished Mar 19 12:28:25 PM PDT 24
Peak memory 206372 kb
Host smart-2a7dbd13-e9c5-4525-8614-a5a411b4c87a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294173580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2294173580 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.2049137352
Short name T1201
Test name
Test status
Simulation time 14149858 ps
CPU time 0.76 seconds
Started Mar 19 12:28:32 PM PDT 24
Finished Mar 19 12:28:34 PM PDT 24
Peak memory 206276 kb
Host smart-36c3bdf8-1cc8-4086-8b19-9119df1c819c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049137352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.2049137352 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1715170565
Short name T1231
Test name
Test status
Simulation time 169857813 ps
CPU time 2.31 seconds
Started Mar 19 12:28:30 PM PDT 24
Finished Mar 19 12:28:32 PM PDT 24
Peak memory 214668 kb
Host smart-a5d73a64-8f41-4a1b-a31b-65eb4f65bb5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715170565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.1715170565 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2202473857
Short name T1207
Test name
Test status
Simulation time 69009688 ps
CPU time 1.18 seconds
Started Mar 19 12:28:31 PM PDT 24
Finished Mar 19 12:28:33 PM PDT 24
Peak memory 215128 kb
Host smart-e9dbdd67-3c86-45c4-8d6a-ae64ec6aa477
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202473857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.2202473857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1667048849
Short name T1151
Test name
Test status
Simulation time 59116248 ps
CPU time 2.35 seconds
Started Mar 19 12:28:45 PM PDT 24
Finished Mar 19 12:28:47 PM PDT 24
Peak memory 214976 kb
Host smart-3cb29fb3-b888-448d-bf24-f0c969938192
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667048849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.1667048849 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2265886780
Short name T1176
Test name
Test status
Simulation time 228864601 ps
CPU time 1.85 seconds
Started Mar 19 12:28:16 PM PDT 24
Finished Mar 19 12:28:18 PM PDT 24
Peak memory 222820 kb
Host smart-da3adb46-8f98-4be4-ae49-896477905723
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265886780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2265886780 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.4186544230
Short name T179
Test name
Test status
Simulation time 137636447 ps
CPU time 4.18 seconds
Started Mar 19 12:28:31 PM PDT 24
Finished Mar 19 12:28:35 PM PDT 24
Peak memory 214608 kb
Host smart-c18246ec-b763-4de9-be44-b084a233a85d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186544230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.41865
44230 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3041208307
Short name T1158
Test name
Test status
Simulation time 80628789 ps
CPU time 2.25 seconds
Started Mar 19 12:28:39 PM PDT 24
Finished Mar 19 12:28:41 PM PDT 24
Peak memory 222716 kb
Host smart-b717a452-9328-4a7a-ba53-898574e95e82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041208307 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.3041208307 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2747429444
Short name T1128
Test name
Test status
Simulation time 103615432 ps
CPU time 1.16 seconds
Started Mar 19 12:28:26 PM PDT 24
Finished Mar 19 12:28:27 PM PDT 24
Peak memory 206368 kb
Host smart-9f0ecc6d-7df4-4784-8927-be3fc764a8ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747429444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.2747429444 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.2706551689
Short name T1170
Test name
Test status
Simulation time 14426008 ps
CPU time 0.74 seconds
Started Mar 19 12:28:37 PM PDT 24
Finished Mar 19 12:28:38 PM PDT 24
Peak memory 206280 kb
Host smart-4bb893e6-17ec-428f-9b49-7c78bc1da35a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706551689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.2706551689 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2277844749
Short name T1108
Test name
Test status
Simulation time 229287895 ps
CPU time 1.5 seconds
Started Mar 19 12:28:13 PM PDT 24
Finished Mar 19 12:28:15 PM PDT 24
Peak memory 214792 kb
Host smart-ff439af1-c091-4e6a-9684-60fe0516a520
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277844749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.2277844749 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.838388037
Short name T98
Test name
Test status
Simulation time 43728706 ps
CPU time 1.37 seconds
Started Mar 19 12:28:19 PM PDT 24
Finished Mar 19 12:28:21 PM PDT 24
Peak memory 214900 kb
Host smart-51c991fc-73d5-461a-997f-5b42fc95cb5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838388037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_e
rrors.838388037 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.828110051
Short name T1180
Test name
Test status
Simulation time 103514235 ps
CPU time 2.58 seconds
Started Mar 19 12:28:37 PM PDT 24
Finished Mar 19 12:28:40 PM PDT 24
Peak memory 214940 kb
Host smart-7d1da14c-b9d5-4b74-91c8-c92a870b06f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828110051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_
shadow_reg_errors_with_csr_rw.828110051 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.421316462
Short name T1149
Test name
Test status
Simulation time 153296437 ps
CPU time 2.56 seconds
Started Mar 19 12:28:48 PM PDT 24
Finished Mar 19 12:28:51 PM PDT 24
Peak memory 214808 kb
Host smart-6aaa41fb-1568-45cb-a8eb-902e8c2905a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421316462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.421316462 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3923707225
Short name T114
Test name
Test status
Simulation time 79050655 ps
CPU time 2.51 seconds
Started Mar 19 12:28:34 PM PDT 24
Finished Mar 19 12:28:37 PM PDT 24
Peak memory 206368 kb
Host smart-07ea473c-6dc6-464b-bc18-c1ad2f43b504
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923707225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.39237
07225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2123007642
Short name T1130
Test name
Test status
Simulation time 65421086 ps
CPU time 2.22 seconds
Started Mar 19 12:28:15 PM PDT 24
Finished Mar 19 12:28:17 PM PDT 24
Peak memory 222732 kb
Host smart-b5accf6c-309f-425f-9861-f409a7c7f198
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123007642 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.2123007642 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.1294013642
Short name T1133
Test name
Test status
Simulation time 27277802 ps
CPU time 0.97 seconds
Started Mar 19 12:28:14 PM PDT 24
Finished Mar 19 12:28:16 PM PDT 24
Peak memory 206284 kb
Host smart-8a9f18d1-a781-4246-9624-5763ed50d6f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294013642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.1294013642 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.3053029561
Short name T1206
Test name
Test status
Simulation time 16473808 ps
CPU time 0.71 seconds
Started Mar 19 12:28:44 PM PDT 24
Finished Mar 19 12:28:46 PM PDT 24
Peak memory 206276 kb
Host smart-c5d01376-e710-4d77-b72d-ffad92c01fe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053029561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3053029561 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2490951262
Short name T1103
Test name
Test status
Simulation time 288058793 ps
CPU time 2.08 seconds
Started Mar 19 12:28:14 PM PDT 24
Finished Mar 19 12:28:17 PM PDT 24
Peak memory 214540 kb
Host smart-b136f072-9b49-48ff-a34e-a659e42333c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490951262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.2490951262 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.496845734
Short name T1203
Test name
Test status
Simulation time 181238528 ps
CPU time 2.45 seconds
Started Mar 19 12:28:36 PM PDT 24
Finished Mar 19 12:28:39 PM PDT 24
Peak memory 215144 kb
Host smart-907d9be7-ab69-4dd6-8e9b-3cd3580b03ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496845734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_
shadow_reg_errors_with_csr_rw.496845734 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.1034613115
Short name T1110
Test name
Test status
Simulation time 86059752 ps
CPU time 2.6 seconds
Started Mar 19 12:28:55 PM PDT 24
Finished Mar 19 12:28:58 PM PDT 24
Peak memory 214712 kb
Host smart-71a100ba-77f6-42dc-a90e-feabc5b940f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034613115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.1034613115 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.296170155
Short name T173
Test name
Test status
Simulation time 618487576 ps
CPU time 3.65 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:28:46 PM PDT 24
Peak memory 214556 kb
Host smart-df65de47-b6d6-459f-8c9a-a0aa738d5bb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296170155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.296170
155 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.3960655825
Short name T1062
Test name
Test status
Simulation time 83694588 ps
CPU time 0.82 seconds
Started Mar 19 01:03:37 PM PDT 24
Finished Mar 19 01:03:42 PM PDT 24
Peak memory 205376 kb
Host smart-d16bd4c1-ace4-4726-9d3d-22457b2fd8b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960655825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.3960655825 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.1732924255
Short name T545
Test name
Test status
Simulation time 3984529097 ps
CPU time 66.09 seconds
Started Mar 19 01:03:27 PM PDT 24
Finished Mar 19 01:04:37 PM PDT 24
Peak memory 227576 kb
Host smart-7f795767-fc6c-4216-9493-36100acac3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732924255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.1732924255 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.1078860666
Short name T613
Test name
Test status
Simulation time 23368084714 ps
CPU time 210.84 seconds
Started Mar 19 01:03:21 PM PDT 24
Finished Mar 19 01:06:52 PM PDT 24
Peak memory 240112 kb
Host smart-42fd95d8-d917-40d5-a805-421709a414ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078860666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.1078860666 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.83401269
Short name T356
Test name
Test status
Simulation time 108048690800 ps
CPU time 851.8 seconds
Started Mar 19 01:03:28 PM PDT 24
Finished Mar 19 01:17:42 PM PDT 24
Peak memory 233544 kb
Host smart-9f4c8099-3edd-4fa4-94c6-fd6e2c069060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83401269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.83401269 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.978892264
Short name T331
Test name
Test status
Simulation time 7413236735 ps
CPU time 32.59 seconds
Started Mar 19 01:03:32 PM PDT 24
Finished Mar 19 01:04:05 PM PDT 24
Peak memory 219960 kb
Host smart-59494595-2576-4f49-a5d7-c8f28bbae22e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=978892264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.978892264 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.681084556
Short name T633
Test name
Test status
Simulation time 271631998 ps
CPU time 18.28 seconds
Started Mar 19 01:03:34 PM PDT 24
Finished Mar 19 01:03:52 PM PDT 24
Peak memory 223836 kb
Host smart-19a3c419-d12d-4781-94b3-3842b637d590
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=681084556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.681084556 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.29081807
Short name T439
Test name
Test status
Simulation time 1898873064 ps
CPU time 17.23 seconds
Started Mar 19 01:03:36 PM PDT 24
Finished Mar 19 01:03:53 PM PDT 24
Peak memory 215920 kb
Host smart-fb719bac-0f31-418b-9b4a-6698d451ec16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29081807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.29081807 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.835180250
Short name T388
Test name
Test status
Simulation time 7059316131 ps
CPU time 221.11 seconds
Started Mar 19 01:03:27 PM PDT 24
Finished Mar 19 01:07:12 PM PDT 24
Peak memory 242168 kb
Host smart-6060792e-7c89-4f56-ae53-bb08154b1af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835180250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.835180250 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.2765073408
Short name T722
Test name
Test status
Simulation time 45260893502 ps
CPU time 300.75 seconds
Started Mar 19 01:03:36 PM PDT 24
Finished Mar 19 01:08:39 PM PDT 24
Peak memory 256064 kb
Host smart-41637488-2f8c-49d6-82ae-61ba9348555a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765073408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.2765073408 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.547350048
Short name T716
Test name
Test status
Simulation time 3376731111 ps
CPU time 4.01 seconds
Started Mar 19 01:03:34 PM PDT 24
Finished Mar 19 01:03:38 PM PDT 24
Peak memory 207660 kb
Host smart-5c7649e9-208a-4def-94a1-df65361b8f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547350048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.547350048 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.2151346655
Short name T1083
Test name
Test status
Simulation time 153065690 ps
CPU time 1.29 seconds
Started Mar 19 01:03:37 PM PDT 24
Finished Mar 19 01:03:43 PM PDT 24
Peak memory 215800 kb
Host smart-5510fc01-8bac-4c79-8983-760a1662b4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151346655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2151346655 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.3340310711
Short name T501
Test name
Test status
Simulation time 16998389669 ps
CPU time 1493.2 seconds
Started Mar 19 01:03:23 PM PDT 24
Finished Mar 19 01:28:20 PM PDT 24
Peak memory 378896 kb
Host smart-1395651e-c517-4076-b9f6-0835bdbcbae0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340310711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.3340310711 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.2731022095
Short name T87
Test name
Test status
Simulation time 22248037530 ps
CPU time 213.23 seconds
Started Mar 19 01:03:26 PM PDT 24
Finished Mar 19 01:07:03 PM PDT 24
Peak memory 240336 kb
Host smart-d2e1c52f-62aa-42cc-a1c3-fd2260d433ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731022095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2731022095 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.746036568
Short name T12
Test name
Test status
Simulation time 5891149051 ps
CPU time 29.29 seconds
Started Mar 19 01:03:34 PM PDT 24
Finished Mar 19 01:04:03 PM PDT 24
Peak memory 249964 kb
Host smart-568335ec-9c59-424e-8cd8-2d6bb61b7da7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746036568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.746036568 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.39807444
Short name T312
Test name
Test status
Simulation time 24824701301 ps
CPU time 186.99 seconds
Started Mar 19 01:03:26 PM PDT 24
Finished Mar 19 01:06:37 PM PDT 24
Peak memory 236164 kb
Host smart-ad75782e-eaa0-4830-8a25-5f524cfcaae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39807444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.39807444 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.2419928091
Short name T978
Test name
Test status
Simulation time 3144040256 ps
CPU time 13.87 seconds
Started Mar 19 01:03:23 PM PDT 24
Finished Mar 19 01:03:40 PM PDT 24
Peak memory 224084 kb
Host smart-97dd4b54-6992-4e40-a839-b5edf91f239f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419928091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2419928091 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.735110906
Short name T492
Test name
Test status
Simulation time 67882777342 ps
CPU time 1447.93 seconds
Started Mar 19 01:03:35 PM PDT 24
Finished Mar 19 01:27:43 PM PDT 24
Peak memory 389220 kb
Host smart-1b171595-8cce-4af8-923c-4742ef0c70ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=735110906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.735110906 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.1599881550
Short name T644
Test name
Test status
Simulation time 1015096717 ps
CPU time 3.97 seconds
Started Mar 19 01:03:29 PM PDT 24
Finished Mar 19 01:03:34 PM PDT 24
Peak memory 215992 kb
Host smart-d485625f-c9e8-4764-82da-48dbc5dfc919
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599881550 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.1599881550 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.1523587980
Short name T1057
Test name
Test status
Simulation time 523326213 ps
CPU time 5 seconds
Started Mar 19 01:03:24 PM PDT 24
Finished Mar 19 01:03:35 PM PDT 24
Peak memory 215840 kb
Host smart-90964f3e-2dd7-401c-9e7c-3304a223cdb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523587980 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.1523587980 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.1485891266
Short name T715
Test name
Test status
Simulation time 66462274369 ps
CPU time 1736.89 seconds
Started Mar 19 01:03:29 PM PDT 24
Finished Mar 19 01:32:27 PM PDT 24
Peak memory 378160 kb
Host smart-4bb83668-ef61-4b22-b64c-8687e3e385c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1485891266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.1485891266 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.4170434268
Short name T208
Test name
Test status
Simulation time 17287844062 ps
CPU time 1426.75 seconds
Started Mar 19 01:03:28 PM PDT 24
Finished Mar 19 01:27:17 PM PDT 24
Peak memory 364928 kb
Host smart-048e082b-5b98-440e-be0f-eef410788972
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4170434268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.4170434268 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.3826649109
Short name T648
Test name
Test status
Simulation time 13917529756 ps
CPU time 1098.31 seconds
Started Mar 19 01:03:24 PM PDT 24
Finished Mar 19 01:21:48 PM PDT 24
Peak memory 328800 kb
Host smart-1137ffa1-6aeb-4752-9b98-d4b563fd1935
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3826649109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.3826649109 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.754906912
Short name T956
Test name
Test status
Simulation time 39323749304 ps
CPU time 781.44 seconds
Started Mar 19 01:03:27 PM PDT 24
Finished Mar 19 01:16:32 PM PDT 24
Peak memory 293736 kb
Host smart-de07734f-082d-4fc3-b6d3-a5bd752eec6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=754906912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.754906912 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.3916670593
Short name T628
Test name
Test status
Simulation time 2119561931097 ps
CPU time 4605.86 seconds
Started Mar 19 01:03:25 PM PDT 24
Finished Mar 19 02:20:16 PM PDT 24
Peak memory 637616 kb
Host smart-3179094d-5368-4e31-b382-3eb14555c67d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3916670593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.3916670593 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.3851798485
Short name T480
Test name
Test status
Simulation time 91989307203 ps
CPU time 3583.21 seconds
Started Mar 19 01:03:26 PM PDT 24
Finished Mar 19 02:03:14 PM PDT 24
Peak memory 560976 kb
Host smart-2ec97212-21e2-4398-a11e-2427320af450
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3851798485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.3851798485 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.2802946391
Short name T340
Test name
Test status
Simulation time 25393640 ps
CPU time 0.75 seconds
Started Mar 19 01:03:41 PM PDT 24
Finished Mar 19 01:03:42 PM PDT 24
Peak memory 205396 kb
Host smart-8e45e43d-4c7f-4ded-8947-5b5b069e9155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802946391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2802946391 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.2643997179
Short name T27
Test name
Test status
Simulation time 1463693646 ps
CPU time 88.13 seconds
Started Mar 19 01:03:44 PM PDT 24
Finished Mar 19 01:05:12 PM PDT 24
Peak memory 229368 kb
Host smart-60f5dc62-c398-493a-98b6-53f2e8f13809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643997179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.2643997179 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.1567366937
Short name T928
Test name
Test status
Simulation time 1945700094 ps
CPU time 65.38 seconds
Started Mar 19 01:03:32 PM PDT 24
Finished Mar 19 01:04:37 PM PDT 24
Peak memory 225864 kb
Host smart-289fb27c-a0d1-47c5-954f-ffb16e562e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567366937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.1567366937 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.1798182048
Short name T355
Test name
Test status
Simulation time 30273368329 ps
CPU time 453.22 seconds
Started Mar 19 01:03:42 PM PDT 24
Finished Mar 19 01:11:15 PM PDT 24
Peak memory 238616 kb
Host smart-87148353-2db4-45ab-94f9-1bd88c504e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798182048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.1798182048 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.3905741447
Short name T297
Test name
Test status
Simulation time 1232047961 ps
CPU time 32.18 seconds
Started Mar 19 01:03:44 PM PDT 24
Finished Mar 19 01:04:16 PM PDT 24
Peak memory 225192 kb
Host smart-31e11180-e3a9-4b5b-a64b-06244970600c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3905741447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3905741447 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.1621113382
Short name T190
Test name
Test status
Simulation time 884906885 ps
CPU time 3.35 seconds
Started Mar 19 01:03:44 PM PDT 24
Finished Mar 19 01:03:47 PM PDT 24
Peak memory 218876 kb
Host smart-2266ae34-392a-4c86-b9da-165051f7d120
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1621113382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1621113382 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.2092278612
Short name T817
Test name
Test status
Simulation time 7424488951 ps
CPU time 65.9 seconds
Started Mar 19 01:03:40 PM PDT 24
Finished Mar 19 01:04:47 PM PDT 24
Peak memory 217120 kb
Host smart-bbe0f605-c717-42f9-b25b-64e59b301baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092278612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.2092278612 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.1733238547
Short name T602
Test name
Test status
Simulation time 20685709755 ps
CPU time 234.41 seconds
Started Mar 19 01:03:42 PM PDT 24
Finished Mar 19 01:07:37 PM PDT 24
Peak memory 240652 kb
Host smart-9648ba8b-c5d1-4d9b-b650-cf3da56d604a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733238547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.1733238547 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.165917902
Short name T1020
Test name
Test status
Simulation time 42593551439 ps
CPU time 305.06 seconds
Started Mar 19 01:03:41 PM PDT 24
Finished Mar 19 01:08:47 PM PDT 24
Peak memory 252200 kb
Host smart-8772596f-8a6b-483c-b163-a23795ba8c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165917902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.165917902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.1905987330
Short name T383
Test name
Test status
Simulation time 1393607160 ps
CPU time 2.22 seconds
Started Mar 19 01:03:45 PM PDT 24
Finished Mar 19 01:03:47 PM PDT 24
Peak memory 207192 kb
Host smart-be0fb5f1-6813-4213-b6b5-53c72ec81d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905987330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.1905987330 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.296151217
Short name T992
Test name
Test status
Simulation time 185465434 ps
CPU time 2.34 seconds
Started Mar 19 01:03:41 PM PDT 24
Finished Mar 19 01:03:44 PM PDT 24
Peak memory 219052 kb
Host smart-63e849c7-8eab-41d1-94ed-657184f6c6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296151217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.296151217 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.3221976553
Short name T916
Test name
Test status
Simulation time 83081949484 ps
CPU time 534.52 seconds
Started Mar 19 01:03:33 PM PDT 24
Finished Mar 19 01:12:28 PM PDT 24
Peak memory 273388 kb
Host smart-4315b4b3-0059-4e29-9685-001f33cc9b32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221976553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.3221976553 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.3213968209
Short name T651
Test name
Test status
Simulation time 18753610290 ps
CPU time 112.07 seconds
Started Mar 19 01:03:40 PM PDT 24
Finished Mar 19 01:05:34 PM PDT 24
Peak memory 231880 kb
Host smart-23ba7db3-e957-417a-884d-2b33db3f69f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213968209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3213968209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sideload.1315106407
Short name T195
Test name
Test status
Simulation time 3400041815 ps
CPU time 120.66 seconds
Started Mar 19 01:03:33 PM PDT 24
Finished Mar 19 01:05:34 PM PDT 24
Peak memory 232784 kb
Host smart-df533161-398f-47a9-a5c8-bb5c121df92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315106407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1315106407 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.1560082250
Short name T993
Test name
Test status
Simulation time 4674104385 ps
CPU time 32.75 seconds
Started Mar 19 01:03:33 PM PDT 24
Finished Mar 19 01:04:06 PM PDT 24
Peak memory 219596 kb
Host smart-dd2ba8d6-73ee-4978-b974-9d2d3c4a10b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560082250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.1560082250 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.1036303399
Short name T942
Test name
Test status
Simulation time 483202615 ps
CPU time 33.66 seconds
Started Mar 19 01:03:40 PM PDT 24
Finished Mar 19 01:04:15 PM PDT 24
Peak memory 220248 kb
Host smart-f3442104-d959-42b4-a8b9-546cf0500c0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1036303399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.1036303399 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.1747591877
Short name T906
Test name
Test status
Simulation time 189847796 ps
CPU time 4.16 seconds
Started Mar 19 01:03:37 PM PDT 24
Finished Mar 19 01:03:45 PM PDT 24
Peak memory 215904 kb
Host smart-98a81dd7-5040-44c1-bdfb-66f1ffe24aef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747591877 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.1747591877 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.1157589147
Short name T18
Test name
Test status
Simulation time 222488898 ps
CPU time 5 seconds
Started Mar 19 01:03:37 PM PDT 24
Finished Mar 19 01:03:46 PM PDT 24
Peak memory 215992 kb
Host smart-959ece4a-e7ec-4cd8-aabe-fe1953d33617
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157589147 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.1157589147 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.937165966
Short name T1025
Test name
Test status
Simulation time 19296157103 ps
CPU time 1518.52 seconds
Started Mar 19 01:03:40 PM PDT 24
Finished Mar 19 01:29:00 PM PDT 24
Peak memory 389960 kb
Host smart-d6b9953f-6806-4a33-bc90-a5ed472c718a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=937165966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.937165966 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.2420373793
Short name T70
Test name
Test status
Simulation time 362333401684 ps
CPU time 1875.89 seconds
Started Mar 19 01:03:33 PM PDT 24
Finished Mar 19 01:34:49 PM PDT 24
Peak memory 377136 kb
Host smart-b61f295a-5445-4d3f-b177-924e62f12969
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2420373793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.2420373793 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.589555635
Short name T40
Test name
Test status
Simulation time 14115684880 ps
CPU time 1105.87 seconds
Started Mar 19 01:03:37 PM PDT 24
Finished Mar 19 01:22:07 PM PDT 24
Peak memory 333416 kb
Host smart-fa0ed5ef-2810-467d-b8e3-c3dddc1662f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=589555635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.589555635 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.2840402074
Short name T820
Test name
Test status
Simulation time 10100795107 ps
CPU time 774.36 seconds
Started Mar 19 01:03:34 PM PDT 24
Finished Mar 19 01:16:29 PM PDT 24
Peak memory 294900 kb
Host smart-f65b5d8f-3f27-44c1-93e3-caa4aca7f84c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2840402074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.2840402074 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.536849433
Short name T79
Test name
Test status
Simulation time 170498794451 ps
CPU time 4703.67 seconds
Started Mar 19 01:03:37 PM PDT 24
Finished Mar 19 02:22:05 PM PDT 24
Peak memory 643596 kb
Host smart-2dbef1b1-3213-4df7-888d-9f72644e0a43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=536849433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.536849433 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.1895978015
Short name T285
Test name
Test status
Simulation time 607536442357 ps
CPU time 4292.27 seconds
Started Mar 19 01:03:35 PM PDT 24
Finished Mar 19 02:15:08 PM PDT 24
Peak memory 564008 kb
Host smart-c55deb30-3cf9-4cfc-9358-69d9941b7539
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1895978015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1895978015 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_app.3351260013
Short name T522
Test name
Test status
Simulation time 5281424780 ps
CPU time 93.19 seconds
Started Mar 19 01:04:26 PM PDT 24
Finished Mar 19 01:05:59 PM PDT 24
Peak memory 229256 kb
Host smart-f2f5ddfd-c55c-4e59-9464-9303da734ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351260013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.3351260013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.2676523285
Short name T1024
Test name
Test status
Simulation time 25567327204 ps
CPU time 568.52 seconds
Started Mar 19 01:04:32 PM PDT 24
Finished Mar 19 01:14:00 PM PDT 24
Peak memory 230588 kb
Host smart-27e492a3-9d83-41c9-a0ed-8ba031d72251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676523285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.2676523285 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.2956376700
Short name T709
Test name
Test status
Simulation time 60160174 ps
CPU time 1.98 seconds
Started Mar 19 01:04:37 PM PDT 24
Finished Mar 19 01:04:39 PM PDT 24
Peak memory 218472 kb
Host smart-34a7c306-a2d9-4f1d-9e60-38c1e45e93eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2956376700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2956376700 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.4087196171
Short name T459
Test name
Test status
Simulation time 583229584 ps
CPU time 20.53 seconds
Started Mar 19 01:04:51 PM PDT 24
Finished Mar 19 01:05:13 PM PDT 24
Peak memory 223680 kb
Host smart-8701e5be-aea0-457b-a580-aab7a46a41f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4087196171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.4087196171 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.984209968
Short name T30
Test name
Test status
Simulation time 66685078070 ps
CPU time 159.93 seconds
Started Mar 19 01:04:37 PM PDT 24
Finished Mar 19 01:07:17 PM PDT 24
Peak memory 232580 kb
Host smart-4cb5720a-05fd-4af4-b630-034ac6e38139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984209968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.984209968 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.2179460057
Short name T296
Test name
Test status
Simulation time 4801081111 ps
CPU time 370.51 seconds
Started Mar 19 01:04:36 PM PDT 24
Finished Mar 19 01:10:48 PM PDT 24
Peak memory 256872 kb
Host smart-6bee08ab-0244-4765-a5ce-0e3b1548ab1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179460057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.2179460057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.332259728
Short name T975
Test name
Test status
Simulation time 3727315851 ps
CPU time 6.14 seconds
Started Mar 19 01:04:35 PM PDT 24
Finished Mar 19 01:04:41 PM PDT 24
Peak memory 207720 kb
Host smart-e94cea95-a722-4a23-8b3c-fbe28bf2da73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332259728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.332259728 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.981619285
Short name T850
Test name
Test status
Simulation time 104734204 ps
CPU time 1.35 seconds
Started Mar 19 01:04:35 PM PDT 24
Finished Mar 19 01:04:37 PM PDT 24
Peak memory 216892 kb
Host smart-70a75f82-774c-4f14-9916-00f4b1ed6488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981619285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.981619285 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.4081990635
Short name T957
Test name
Test status
Simulation time 173411070980 ps
CPU time 2659.81 seconds
Started Mar 19 01:04:27 PM PDT 24
Finished Mar 19 01:48:48 PM PDT 24
Peak memory 472088 kb
Host smart-331c40bc-7a54-46c8-a204-cb0a392d25bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081990635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.4081990635 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.4046725259
Short name T994
Test name
Test status
Simulation time 95833212332 ps
CPU time 374.8 seconds
Started Mar 19 01:04:27 PM PDT 24
Finished Mar 19 01:10:42 PM PDT 24
Peak memory 249764 kb
Host smart-42180e1f-5477-4140-b48b-06dbe36201f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046725259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.4046725259 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.301765501
Short name T429
Test name
Test status
Simulation time 2645277580 ps
CPU time 52.97 seconds
Started Mar 19 01:04:32 PM PDT 24
Finished Mar 19 01:05:25 PM PDT 24
Peak memory 219732 kb
Host smart-3f53c7cb-db05-4202-b690-d242e11e3da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301765501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.301765501 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.3983587095
Short name T73
Test name
Test status
Simulation time 75834622898 ps
CPU time 1515.09 seconds
Started Mar 19 01:04:51 PM PDT 24
Finished Mar 19 01:30:08 PM PDT 24
Peak memory 394736 kb
Host smart-3598a436-6b78-44ca-a523-91ba1dc4eef5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3983587095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.3983587095 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.3381719222
Short name T224
Test name
Test status
Simulation time 69724129 ps
CPU time 4.21 seconds
Started Mar 19 01:04:28 PM PDT 24
Finished Mar 19 01:04:32 PM PDT 24
Peak memory 215932 kb
Host smart-1539d04c-c6ab-48c6-8311-87155561ce76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381719222 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.kmac_test_vectors_kmac.3381719222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.3196353675
Short name T712
Test name
Test status
Simulation time 241778492 ps
CPU time 4.61 seconds
Started Mar 19 01:04:25 PM PDT 24
Finished Mar 19 01:04:30 PM PDT 24
Peak memory 215948 kb
Host smart-9e961861-eba0-4979-98cc-aa36c1956d7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196353675 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.kmac_test_vectors_kmac_xof.3196353675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.3368746311
Short name T346
Test name
Test status
Simulation time 134296046179 ps
CPU time 1730.57 seconds
Started Mar 19 01:04:27 PM PDT 24
Finished Mar 19 01:33:18 PM PDT 24
Peak memory 389320 kb
Host smart-b3503a3a-c335-4e89-8d59-72fff0421b59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3368746311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.3368746311 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.778992253
Short name T399
Test name
Test status
Simulation time 382114343941 ps
CPU time 1673.67 seconds
Started Mar 19 01:04:31 PM PDT 24
Finished Mar 19 01:32:25 PM PDT 24
Peak memory 374652 kb
Host smart-b9ca3987-f356-4bf5-8534-6528596a01dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=778992253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.778992253 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.1193371813
Short name T91
Test name
Test status
Simulation time 57216871675 ps
CPU time 1151.64 seconds
Started Mar 19 01:04:26 PM PDT 24
Finished Mar 19 01:23:38 PM PDT 24
Peak memory 337740 kb
Host smart-ed9201d9-75a9-4d3f-8d01-50de022cd5b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1193371813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.1193371813 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.1221706530
Short name T575
Test name
Test status
Simulation time 9851889271 ps
CPU time 752.41 seconds
Started Mar 19 01:04:25 PM PDT 24
Finished Mar 19 01:16:58 PM PDT 24
Peak memory 294448 kb
Host smart-4fb81022-139c-4c7e-a741-6816f042081e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1221706530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.1221706530 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.3888849023
Short name T290
Test name
Test status
Simulation time 593558882989 ps
CPU time 5139.41 seconds
Started Mar 19 01:04:33 PM PDT 24
Finished Mar 19 02:30:13 PM PDT 24
Peak memory 651176 kb
Host smart-226da3b1-8f58-49d4-9c0b-d62fd2766670
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3888849023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.3888849023 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.187577006
Short name T696
Test name
Test status
Simulation time 467111529245 ps
CPU time 4087.3 seconds
Started Mar 19 01:04:25 PM PDT 24
Finished Mar 19 02:12:33 PM PDT 24
Peak memory 553968 kb
Host smart-01f46352-42ef-4d42-b498-2d6cc712c473
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=187577006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.187577006 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_alert_test.2626562058
Short name T948
Test name
Test status
Simulation time 32112026 ps
CPU time 0.72 seconds
Started Mar 19 01:04:35 PM PDT 24
Finished Mar 19 01:04:36 PM PDT 24
Peak memory 205304 kb
Host smart-bf1c40a6-67d0-4c25-8569-b5636d9bcd3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626562058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.2626562058 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_burst_write.3243410678
Short name T910
Test name
Test status
Simulation time 35072945014 ps
CPU time 704.66 seconds
Started Mar 19 01:04:35 PM PDT 24
Finished Mar 19 01:16:21 PM PDT 24
Peak memory 232652 kb
Host smart-ebc45e0a-189c-49d4-8b69-affb55f1b125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243410678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.3243410678 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.954267687
Short name T411
Test name
Test status
Simulation time 305824169 ps
CPU time 22.41 seconds
Started Mar 19 01:04:51 PM PDT 24
Finished Mar 19 01:05:15 PM PDT 24
Peak memory 220320 kb
Host smart-e70f1de6-8b1e-4e02-b859-2876e9fb9f55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=954267687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.954267687 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.771156361
Short name T561
Test name
Test status
Simulation time 1651817013 ps
CPU time 29.87 seconds
Started Mar 19 01:04:36 PM PDT 24
Finished Mar 19 01:05:07 PM PDT 24
Peak memory 225500 kb
Host smart-d58fd57a-ab22-4b85-b1e2-5a427e9c2d99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=771156361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.771156361 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.1646843771
Short name T968
Test name
Test status
Simulation time 10951230801 ps
CPU time 49.27 seconds
Started Mar 19 01:04:40 PM PDT 24
Finished Mar 19 01:05:30 PM PDT 24
Peak memory 224220 kb
Host smart-1b703a79-3253-4210-b40f-36bdab2c1543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646843771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.1646843771 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.2183619837
Short name T1023
Test name
Test status
Simulation time 9956065306 ps
CPU time 71.22 seconds
Started Mar 19 01:04:36 PM PDT 24
Finished Mar 19 01:05:47 PM PDT 24
Peak memory 235592 kb
Host smart-913a8e58-5855-4a88-8913-b5421a093275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183619837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.2183619837 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.3695178538
Short name T784
Test name
Test status
Simulation time 3514002288 ps
CPU time 5 seconds
Started Mar 19 01:04:52 PM PDT 24
Finished Mar 19 01:04:57 PM PDT 24
Peak memory 207536 kb
Host smart-bc11796e-c820-4246-bc40-e6a57a8d1101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695178538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.3695178538 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.2778634884
Short name T260
Test name
Test status
Simulation time 107364328 ps
CPU time 1.39 seconds
Started Mar 19 01:04:36 PM PDT 24
Finished Mar 19 01:04:37 PM PDT 24
Peak memory 215904 kb
Host smart-903a4816-bbb9-4df3-9819-dd47712c1fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778634884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.2778634884 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.1012605487
Short name T1036
Test name
Test status
Simulation time 26783126466 ps
CPU time 2242.82 seconds
Started Mar 19 01:04:51 PM PDT 24
Finished Mar 19 01:42:15 PM PDT 24
Peak memory 462988 kb
Host smart-503277ea-70b9-4d9e-b94a-5a113b275216
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012605487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.1012605487 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.882818080
Short name T521
Test name
Test status
Simulation time 74085992956 ps
CPU time 413.13 seconds
Started Mar 19 01:04:51 PM PDT 24
Finished Mar 19 01:11:46 PM PDT 24
Peak memory 247132 kb
Host smart-c9b3177c-a22c-4ce8-8252-ff5c59a9f2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882818080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.882818080 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.2313493770
Short name T570
Test name
Test status
Simulation time 7863928369 ps
CPU time 35.65 seconds
Started Mar 19 01:04:36 PM PDT 24
Finished Mar 19 01:05:12 PM PDT 24
Peak memory 216212 kb
Host smart-0e0a138a-d689-41cf-a52d-e9537ea90124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313493770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.2313493770 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.3556405931
Short name T625
Test name
Test status
Simulation time 44929356996 ps
CPU time 1028.03 seconds
Started Mar 19 01:04:37 PM PDT 24
Finished Mar 19 01:21:45 PM PDT 24
Peak memory 332740 kb
Host smart-23b13e32-9d9d-4960-8a6b-bc54b277ff07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3556405931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.3556405931 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.4118857255
Short name T819
Test name
Test status
Simulation time 248562797 ps
CPU time 5 seconds
Started Mar 19 01:04:35 PM PDT 24
Finished Mar 19 01:04:41 PM PDT 24
Peak memory 215972 kb
Host smart-8ce3eb42-c5b7-433f-be89-a665201f571f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118857255 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.4118857255 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.904377506
Short name T238
Test name
Test status
Simulation time 68262400 ps
CPU time 3.83 seconds
Started Mar 19 01:04:35 PM PDT 24
Finished Mar 19 01:04:39 PM PDT 24
Peak memory 215948 kb
Host smart-d02205be-6c17-4934-9a68-3ddbdc211998
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904377506 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.kmac_test_vectors_kmac_xof.904377506 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.64290153
Short name T849
Test name
Test status
Simulation time 399373365906 ps
CPU time 2010.38 seconds
Started Mar 19 01:04:40 PM PDT 24
Finished Mar 19 01:38:11 PM PDT 24
Peak memory 387464 kb
Host smart-b8738562-c75b-4d19-ae2e-4dd7c6ec617a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=64290153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.64290153 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.2514113773
Short name T743
Test name
Test status
Simulation time 398896031348 ps
CPU time 1976.74 seconds
Started Mar 19 01:04:36 PM PDT 24
Finished Mar 19 01:37:33 PM PDT 24
Peak memory 375516 kb
Host smart-75e653cb-b6c8-48ad-b8d0-7ef29f4f81a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2514113773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.2514113773 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.2672492005
Short name T954
Test name
Test status
Simulation time 198085803642 ps
CPU time 1399 seconds
Started Mar 19 01:04:36 PM PDT 24
Finished Mar 19 01:27:55 PM PDT 24
Peak memory 338428 kb
Host smart-bfea2dfa-d7a6-48e4-ba70-60fb2b30d80d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2672492005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.2672492005 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.2337157731
Short name T775
Test name
Test status
Simulation time 31706813125 ps
CPU time 831.85 seconds
Started Mar 19 01:04:36 PM PDT 24
Finished Mar 19 01:18:28 PM PDT 24
Peak memory 289732 kb
Host smart-38961a4a-08d1-4cfa-9965-4ec56063fd11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2337157731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.2337157731 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.1382701212
Short name T403
Test name
Test status
Simulation time 281805934504 ps
CPU time 4138.73 seconds
Started Mar 19 01:04:50 PM PDT 24
Finished Mar 19 02:13:51 PM PDT 24
Peak memory 648164 kb
Host smart-6733c043-0e4a-4d80-8dad-0d98d3c25e82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1382701212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.1382701212 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.2225450524
Short name T347
Test name
Test status
Simulation time 720642916148 ps
CPU time 3746.41 seconds
Started Mar 19 01:04:40 PM PDT 24
Finished Mar 19 02:07:07 PM PDT 24
Peak memory 561020 kb
Host smart-653855c9-f7be-4b5f-844d-9733e58a6d76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2225450524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.2225450524 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.2505284434
Short name T738
Test name
Test status
Simulation time 231852632 ps
CPU time 0.79 seconds
Started Mar 19 01:04:45 PM PDT 24
Finished Mar 19 01:04:46 PM PDT 24
Peak memory 205396 kb
Host smart-8526cd25-0203-4990-802a-a8b77fccfcb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505284434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2505284434 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.4159306276
Short name T556
Test name
Test status
Simulation time 10234162620 ps
CPU time 176.46 seconds
Started Mar 19 01:04:45 PM PDT 24
Finished Mar 19 01:07:41 PM PDT 24
Peak memory 235736 kb
Host smart-5195a46f-a682-4610-9337-2ebb8128efd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159306276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.4159306276 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.3279549307
Short name T438
Test name
Test status
Simulation time 23995188732 ps
CPU time 520.46 seconds
Started Mar 19 01:04:43 PM PDT 24
Finished Mar 19 01:13:24 PM PDT 24
Peak memory 230576 kb
Host smart-1c3238ea-7682-4124-b0a5-63edf4aa103f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279549307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.3279549307 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.974412342
Short name T533
Test name
Test status
Simulation time 1011154824 ps
CPU time 13.91 seconds
Started Mar 19 01:04:47 PM PDT 24
Finished Mar 19 01:05:04 PM PDT 24
Peak memory 223812 kb
Host smart-3eef0b81-f28f-44a4-9d03-a01a65a41ad1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=974412342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.974412342 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.3702615760
Short name T737
Test name
Test status
Simulation time 70978045 ps
CPU time 4.89 seconds
Started Mar 19 01:04:47 PM PDT 24
Finished Mar 19 01:04:55 PM PDT 24
Peak memory 223248 kb
Host smart-2ef54400-1ce2-46fe-96d2-9a414d08e5f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3702615760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3702615760 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.2528912268
Short name T655
Test name
Test status
Simulation time 24027685967 ps
CPU time 165.01 seconds
Started Mar 19 01:04:45 PM PDT 24
Finished Mar 19 01:07:35 PM PDT 24
Peak memory 237184 kb
Host smart-f8557d68-1fbd-462f-94fa-91cf4eb1ee4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528912268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.2528912268 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.610106322
Short name T33
Test name
Test status
Simulation time 3966251719 ps
CPU time 92.49 seconds
Started Mar 19 01:04:48 PM PDT 24
Finished Mar 19 01:06:23 PM PDT 24
Peak memory 237240 kb
Host smart-f0ddf73a-70c7-48e7-ae11-3e72e141a4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610106322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.610106322 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.318931133
Short name T64
Test name
Test status
Simulation time 231089036 ps
CPU time 1.67 seconds
Started Mar 19 01:04:44 PM PDT 24
Finished Mar 19 01:04:45 PM PDT 24
Peak memory 207076 kb
Host smart-4b2293ae-2d37-44a5-8499-5fcae4debee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318931133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.318931133 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.2857659946
Short name T5
Test name
Test status
Simulation time 33797368 ps
CPU time 1.23 seconds
Started Mar 19 01:04:45 PM PDT 24
Finished Mar 19 01:04:46 PM PDT 24
Peak memory 215828 kb
Host smart-c4f1d4bf-58f7-47d5-9add-9d14ae71799a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857659946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.2857659946 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.326573076
Short name T1014
Test name
Test status
Simulation time 454387198036 ps
CPU time 2225.13 seconds
Started Mar 19 01:04:36 PM PDT 24
Finished Mar 19 01:41:42 PM PDT 24
Peak memory 428692 kb
Host smart-4998ec6b-169c-40a3-b531-6c0fe6b7f642
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326573076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_an
d_output.326573076 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.1001794331
Short name T929
Test name
Test status
Simulation time 54091389534 ps
CPU time 289.49 seconds
Started Mar 19 01:04:50 PM PDT 24
Finished Mar 19 01:09:41 PM PDT 24
Peak memory 239840 kb
Host smart-54d5acce-0dec-4b23-b875-4a4ef53e72f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001794331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1001794331 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.1584288
Short name T983
Test name
Test status
Simulation time 268525185 ps
CPU time 3.44 seconds
Started Mar 19 01:04:35 PM PDT 24
Finished Mar 19 01:04:39 PM PDT 24
Peak memory 224068 kb
Host smart-c8a3880d-2059-4f69-a07c-4949917f221f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.1584288 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.3723772763
Short name T543
Test name
Test status
Simulation time 25465356742 ps
CPU time 497.76 seconds
Started Mar 19 01:04:44 PM PDT 24
Finished Mar 19 01:13:02 PM PDT 24
Peak memory 295280 kb
Host smart-71ed0944-d592-4feb-9b79-15baf909cd67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3723772763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.3723772763 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.2442537299
Short name T523
Test name
Test status
Simulation time 409604982 ps
CPU time 4.4 seconds
Started Mar 19 01:04:49 PM PDT 24
Finished Mar 19 01:04:55 PM PDT 24
Peak memory 215988 kb
Host smart-dec51a71-4241-44f8-8bd0-de3788eeaf67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442537299 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.2442537299 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.3573539684
Short name T577
Test name
Test status
Simulation time 245447106 ps
CPU time 3.6 seconds
Started Mar 19 01:04:45 PM PDT 24
Finished Mar 19 01:04:49 PM PDT 24
Peak memory 215896 kb
Host smart-7829ce6d-44f8-4545-8e29-1405ffde2b90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573539684 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.kmac_test_vectors_kmac_xof.3573539684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.323664956
Short name T894
Test name
Test status
Simulation time 128963000563 ps
CPU time 1894.38 seconds
Started Mar 19 01:04:35 PM PDT 24
Finished Mar 19 01:36:10 PM PDT 24
Peak memory 389924 kb
Host smart-122ab804-7c14-4436-9796-ccd12db25721
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=323664956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.323664956 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.874395206
Short name T1077
Test name
Test status
Simulation time 36358329449 ps
CPU time 1380.81 seconds
Started Mar 19 01:04:45 PM PDT 24
Finished Mar 19 01:27:51 PM PDT 24
Peak memory 367904 kb
Host smart-bbf5b5f8-bc26-4a7d-8fa2-546d7c6181f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=874395206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.874395206 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.3954568243
Short name T963
Test name
Test status
Simulation time 18710046719 ps
CPU time 1119.41 seconds
Started Mar 19 01:04:45 PM PDT 24
Finished Mar 19 01:23:24 PM PDT 24
Peak memory 332284 kb
Host smart-0ac987e5-70fd-42eb-94c7-40499d8d1413
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3954568243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.3954568243 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.2756004311
Short name T454
Test name
Test status
Simulation time 9350839149 ps
CPU time 761.87 seconds
Started Mar 19 01:04:44 PM PDT 24
Finished Mar 19 01:17:27 PM PDT 24
Peak memory 291452 kb
Host smart-cc1eaf72-5c25-4fe0-b591-1051302c9a90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2756004311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.2756004311 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.2303391480
Short name T218
Test name
Test status
Simulation time 108990984691 ps
CPU time 3966.74 seconds
Started Mar 19 01:04:44 PM PDT 24
Finished Mar 19 02:10:51 PM PDT 24
Peak memory 658032 kb
Host smart-546536a2-3c88-460a-97bf-5777a3753568
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2303391480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.2303391480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.3750548050
Short name T444
Test name
Test status
Simulation time 146060907497 ps
CPU time 3914.79 seconds
Started Mar 19 01:04:43 PM PDT 24
Finished Mar 19 02:09:59 PM PDT 24
Peak memory 565732 kb
Host smart-0ddbaf6a-ba82-424b-9d7b-a4e0e1d380c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3750548050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.3750548050 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/13.kmac_alert_test.4257794747
Short name T923
Test name
Test status
Simulation time 26010303 ps
CPU time 0.73 seconds
Started Mar 19 01:04:51 PM PDT 24
Finished Mar 19 01:04:53 PM PDT 24
Peak memory 205380 kb
Host smart-96cb273a-d2b7-491a-b867-03b053870f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257794747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.4257794747 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.2300591008
Short name T1022
Test name
Test status
Simulation time 1506547912 ps
CPU time 67.92 seconds
Started Mar 19 01:04:52 PM PDT 24
Finished Mar 19 01:06:01 PM PDT 24
Peak memory 225228 kb
Host smart-b9a0ee6a-6a42-471f-a960-e0814999340e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300591008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2300591008 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.3861176583
Short name T361
Test name
Test status
Simulation time 25539250751 ps
CPU time 749.35 seconds
Started Mar 19 01:04:45 PM PDT 24
Finished Mar 19 01:17:14 PM PDT 24
Peak memory 230848 kb
Host smart-b306df64-aaa2-4359-99d4-3cbe6ea9da5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861176583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.3861176583 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.2701444582
Short name T203
Test name
Test status
Simulation time 763243987 ps
CPU time 10.3 seconds
Started Mar 19 01:04:50 PM PDT 24
Finished Mar 19 01:05:02 PM PDT 24
Peak memory 221960 kb
Host smart-81be3536-54e2-477a-8fae-834f30e50a86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2701444582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2701444582 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.3968785080
Short name T500
Test name
Test status
Simulation time 1588428362 ps
CPU time 38.07 seconds
Started Mar 19 01:04:50 PM PDT 24
Finished Mar 19 01:05:29 PM PDT 24
Peak memory 223916 kb
Host smart-8f650dd0-049c-4f21-b631-8057e61ce25b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3968785080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.3968785080 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.233141572
Short name T866
Test name
Test status
Simulation time 4431712248 ps
CPU time 216.91 seconds
Started Mar 19 01:04:55 PM PDT 24
Finished Mar 19 01:08:32 PM PDT 24
Peak memory 242936 kb
Host smart-a9988ac1-47d8-4b69-a758-e4f0914bf96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233141572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.233141572 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.4072169711
Short name T34
Test name
Test status
Simulation time 3102884549 ps
CPU time 39.15 seconds
Started Mar 19 01:05:08 PM PDT 24
Finished Mar 19 01:05:49 PM PDT 24
Peak memory 232272 kb
Host smart-e16abf2f-af02-4926-8d39-f5d507d4b06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072169711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.4072169711 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.3434532591
Short name T1004
Test name
Test status
Simulation time 304073357 ps
CPU time 1.44 seconds
Started Mar 19 01:05:08 PM PDT 24
Finished Mar 19 01:05:09 PM PDT 24
Peak memory 206568 kb
Host smart-89d2fefd-7dbc-43a6-9b82-d49a67bf79ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434532591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3434532591 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.447938929
Short name T43
Test name
Test status
Simulation time 1798830885 ps
CPU time 29.4 seconds
Started Mar 19 01:04:52 PM PDT 24
Finished Mar 19 01:05:22 PM PDT 24
Peak memory 230200 kb
Host smart-c562f905-f938-47d8-b46e-660c96d22350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447938929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.447938929 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.81470729
Short name T272
Test name
Test status
Simulation time 111426750169 ps
CPU time 2309.54 seconds
Started Mar 19 01:04:45 PM PDT 24
Finished Mar 19 01:43:20 PM PDT 24
Peak memory 464588 kb
Host smart-b35ae255-3e8d-4401-b2eb-735569663546
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81470729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and
_output.81470729 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.2591697869
Short name T196
Test name
Test status
Simulation time 670637809 ps
CPU time 18.85 seconds
Started Mar 19 01:04:45 PM PDT 24
Finished Mar 19 01:05:04 PM PDT 24
Peak memory 220580 kb
Host smart-f9c87ac1-ce5f-4092-9156-bda8613fd688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591697869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.2591697869 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.2781205087
Short name T939
Test name
Test status
Simulation time 3112947930 ps
CPU time 17.02 seconds
Started Mar 19 01:04:46 PM PDT 24
Finished Mar 19 01:05:07 PM PDT 24
Peak memory 222144 kb
Host smart-cad6836a-3be8-45f4-9c16-62286596b8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781205087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.2781205087 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.191120542
Short name T796
Test name
Test status
Simulation time 61174655342 ps
CPU time 1053.1 seconds
Started Mar 19 01:05:09 PM PDT 24
Finished Mar 19 01:22:43 PM PDT 24
Peak memory 348268 kb
Host smart-abb462d1-86e0-4bc7-8d64-edb02aa8f0cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=191120542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.191120542 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.3998390580
Short name T1049
Test name
Test status
Simulation time 331338905 ps
CPU time 4.67 seconds
Started Mar 19 01:04:44 PM PDT 24
Finished Mar 19 01:04:49 PM PDT 24
Peak memory 215940 kb
Host smart-2c712d29-22fe-4262-8e29-ef5211d2a860
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998390580 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.3998390580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.4243305932
Short name T212
Test name
Test status
Simulation time 289436300 ps
CPU time 3.91 seconds
Started Mar 19 01:05:09 PM PDT 24
Finished Mar 19 01:05:13 PM PDT 24
Peak memory 215880 kb
Host smart-6f3b5381-0a6e-4d5e-a16f-ca21e791b247
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243305932 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.4243305932 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.951038639
Short name T863
Test name
Test status
Simulation time 19366820912 ps
CPU time 1466.33 seconds
Started Mar 19 01:04:50 PM PDT 24
Finished Mar 19 01:29:18 PM PDT 24
Peak memory 379364 kb
Host smart-75d3d261-230e-45d4-b8c0-75d290646878
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=951038639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.951038639 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.231359353
Short name T528
Test name
Test status
Simulation time 694523684957 ps
CPU time 2034.6 seconds
Started Mar 19 01:04:46 PM PDT 24
Finished Mar 19 01:38:45 PM PDT 24
Peak memory 389604 kb
Host smart-234900a9-956c-4dac-a5da-0de8744652d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=231359353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.231359353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.2445412489
Short name T713
Test name
Test status
Simulation time 249195648724 ps
CPU time 1338.4 seconds
Started Mar 19 01:04:46 PM PDT 24
Finished Mar 19 01:27:09 PM PDT 24
Peak memory 323464 kb
Host smart-46a2ab92-47b6-4661-86a7-256a604accb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2445412489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.2445412489 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.2797613232
Short name T1059
Test name
Test status
Simulation time 203181240901 ps
CPU time 1068.25 seconds
Started Mar 19 01:04:44 PM PDT 24
Finished Mar 19 01:22:33 PM PDT 24
Peak memory 294392 kb
Host smart-db1439ff-2ce0-43a2-b0be-d3163a54c251
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2797613232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.2797613232 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.3119387960
Short name T611
Test name
Test status
Simulation time 722797865659 ps
CPU time 4697.26 seconds
Started Mar 19 01:04:43 PM PDT 24
Finished Mar 19 02:23:01 PM PDT 24
Peak memory 659864 kb
Host smart-f57c6393-56e0-4741-a0d4-c36594849d18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3119387960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.3119387960 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.3178814946
Short name T229
Test name
Test status
Simulation time 290165499615 ps
CPU time 4068.21 seconds
Started Mar 19 01:04:44 PM PDT 24
Finished Mar 19 02:12:33 PM PDT 24
Peak memory 560332 kb
Host smart-1e30bedc-f31e-4046-aae8-e05435782d71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3178814946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.3178814946 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.3955065903
Short name T1058
Test name
Test status
Simulation time 11938034 ps
CPU time 0.76 seconds
Started Mar 19 01:05:01 PM PDT 24
Finished Mar 19 01:05:02 PM PDT 24
Peak memory 205308 kb
Host smart-3a0b7768-a120-4729-b7fc-faf4e6028713
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955065903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.3955065903 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.3294363272
Short name T436
Test name
Test status
Simulation time 2295207182 ps
CPU time 126.16 seconds
Started Mar 19 01:04:53 PM PDT 24
Finished Mar 19 01:06:59 PM PDT 24
Peak memory 233684 kb
Host smart-009ee0da-18c6-4805-a0b3-fa05c571feed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294363272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.3294363272 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.479512403
Short name T867
Test name
Test status
Simulation time 31520938549 ps
CPU time 728.78 seconds
Started Mar 19 01:04:52 PM PDT 24
Finished Mar 19 01:17:01 PM PDT 24
Peak memory 233292 kb
Host smart-74bef3bc-d302-4edb-816a-81d9716d4387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479512403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.479512403 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.1114131724
Short name T874
Test name
Test status
Simulation time 102883783 ps
CPU time 1.88 seconds
Started Mar 19 01:04:53 PM PDT 24
Finished Mar 19 01:04:55 PM PDT 24
Peak memory 215656 kb
Host smart-4578d689-578d-41d9-bb99-13ab91ad35e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1114131724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.1114131724 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.3240879860
Short name T787
Test name
Test status
Simulation time 2355011111 ps
CPU time 19.4 seconds
Started Mar 19 01:04:52 PM PDT 24
Finished Mar 19 01:05:12 PM PDT 24
Peak memory 223892 kb
Host smart-b2a882b8-b1b6-4694-8ae5-c9bbefc44f54
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3240879860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.3240879860 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.2873614706
Short name T982
Test name
Test status
Simulation time 4195517154 ps
CPU time 74.83 seconds
Started Mar 19 01:04:52 PM PDT 24
Finished Mar 19 01:06:07 PM PDT 24
Peak memory 226320 kb
Host smart-2852e47d-6a82-49ce-b26d-73475c6ff037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873614706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.2873614706 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.9857397
Short name T822
Test name
Test status
Simulation time 36699904136 ps
CPU time 75.45 seconds
Started Mar 19 01:04:55 PM PDT 24
Finished Mar 19 01:06:10 PM PDT 24
Peak memory 234492 kb
Host smart-f446a30b-5dce-4eec-a853-6e303b7ed5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9857397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.9857397 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.380024875
Short name T61
Test name
Test status
Simulation time 630945625 ps
CPU time 3.58 seconds
Started Mar 19 01:05:08 PM PDT 24
Finished Mar 19 01:05:13 PM PDT 24
Peak memory 207512 kb
Host smart-7155bc01-2c92-4b3a-986d-7ded82941e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380024875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.380024875 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.1050100941
Short name T367
Test name
Test status
Simulation time 487185747 ps
CPU time 1.27 seconds
Started Mar 19 01:04:51 PM PDT 24
Finished Mar 19 01:04:54 PM PDT 24
Peak memory 216000 kb
Host smart-339a9f4e-0c16-4513-b694-fc8bc944d2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050100941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.1050100941 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.958931837
Short name T214
Test name
Test status
Simulation time 82684547418 ps
CPU time 2414.85 seconds
Started Mar 19 01:05:08 PM PDT 24
Finished Mar 19 01:45:25 PM PDT 24
Peak memory 450188 kb
Host smart-7265b5e8-0e11-4365-8ce1-d71e784edca0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958931837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_an
d_output.958931837 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.2425576034
Short name T950
Test name
Test status
Simulation time 3834613737 ps
CPU time 68.24 seconds
Started Mar 19 01:04:52 PM PDT 24
Finished Mar 19 01:06:01 PM PDT 24
Peak memory 224664 kb
Host smart-080882cb-de7c-4f2e-90b7-ffe7427f7904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425576034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.2425576034 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.2463482552
Short name T882
Test name
Test status
Simulation time 5967975262 ps
CPU time 23.4 seconds
Started Mar 19 01:05:09 PM PDT 24
Finished Mar 19 01:05:33 PM PDT 24
Peak memory 219752 kb
Host smart-bfef6f30-58f0-43df-926f-f268bb91b532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463482552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.2463482552 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.2276477360
Short name T1048
Test name
Test status
Simulation time 28628757634 ps
CPU time 431 seconds
Started Mar 19 01:04:51 PM PDT 24
Finished Mar 19 01:12:04 PM PDT 24
Peak memory 304424 kb
Host smart-75b094df-7f3b-46ad-ac8f-d7d05c12e91a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2276477360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.2276477360 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.1535165088
Short name T767
Test name
Test status
Simulation time 338548672 ps
CPU time 4.78 seconds
Started Mar 19 01:04:56 PM PDT 24
Finished Mar 19 01:05:01 PM PDT 24
Peak memory 215924 kb
Host smart-a2ca0281-8242-40bd-9619-69b574182c72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535165088 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.kmac_test_vectors_kmac.1535165088 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.791442055
Short name T940
Test name
Test status
Simulation time 248721897 ps
CPU time 3.48 seconds
Started Mar 19 01:04:49 PM PDT 24
Finished Mar 19 01:04:54 PM PDT 24
Peak memory 215932 kb
Host smart-9d58a9bd-2ab5-470e-a9e8-015d2d37a278
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791442055 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.kmac_test_vectors_kmac_xof.791442055 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.2035788956
Short name T922
Test name
Test status
Simulation time 66798593070 ps
CPU time 1876.78 seconds
Started Mar 19 01:04:52 PM PDT 24
Finished Mar 19 01:36:09 PM PDT 24
Peak memory 387704 kb
Host smart-454a93eb-b234-44fd-a54b-c21e77d3366c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2035788956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.2035788956 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.588987028
Short name T406
Test name
Test status
Simulation time 183205924631 ps
CPU time 1879.92 seconds
Started Mar 19 01:04:52 PM PDT 24
Finished Mar 19 01:36:13 PM PDT 24
Peak memory 367300 kb
Host smart-69216223-4ad6-4081-85d3-dcd3d07beaed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=588987028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.588987028 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.3219434006
Short name T364
Test name
Test status
Simulation time 13752664615 ps
CPU time 1078.4 seconds
Started Mar 19 01:04:51 PM PDT 24
Finished Mar 19 01:22:51 PM PDT 24
Peak memory 335124 kb
Host smart-b936d94e-4940-4f9f-a7c9-7f2c87f0e27a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3219434006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.3219434006 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.165322636
Short name T631
Test name
Test status
Simulation time 101762380843 ps
CPU time 983.63 seconds
Started Mar 19 01:05:09 PM PDT 24
Finished Mar 19 01:21:33 PM PDT 24
Peak memory 295256 kb
Host smart-3601aa83-16af-4f46-af5b-e4e0a59205cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=165322636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.165322636 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.406752643
Short name T997
Test name
Test status
Simulation time 641018907949 ps
CPU time 5209.55 seconds
Started Mar 19 01:04:52 PM PDT 24
Finished Mar 19 02:31:43 PM PDT 24
Peak memory 657456 kb
Host smart-52e64976-6975-45a8-8746-c2a52f43eae1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=406752643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.406752643 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.3692129487
Short name T731
Test name
Test status
Simulation time 785993213723 ps
CPU time 3972.93 seconds
Started Mar 19 01:04:53 PM PDT 24
Finished Mar 19 02:11:07 PM PDT 24
Peak memory 563612 kb
Host smart-f2c2bfc4-fb79-4167-8812-ce2a03ca7dc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3692129487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.3692129487 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.3470572724
Short name T815
Test name
Test status
Simulation time 70385104 ps
CPU time 0.82 seconds
Started Mar 19 01:05:04 PM PDT 24
Finished Mar 19 01:05:05 PM PDT 24
Peak memory 205360 kb
Host smart-1687cd89-81a1-43d8-bbb8-21508fbb9f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470572724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3470572724 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.1997465917
Short name T832
Test name
Test status
Simulation time 58620225682 ps
CPU time 306.73 seconds
Started Mar 19 01:05:02 PM PDT 24
Finished Mar 19 01:10:09 PM PDT 24
Peak memory 245556 kb
Host smart-a11a6ec6-9ad1-472c-960d-a9879dae3493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997465917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.1997465917 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.33667135
Short name T511
Test name
Test status
Simulation time 24740977274 ps
CPU time 413.28 seconds
Started Mar 19 01:05:02 PM PDT 24
Finished Mar 19 01:11:56 PM PDT 24
Peak memory 229600 kb
Host smart-f23d1c04-e61b-48c2-b6fc-67cc3f3f8fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33667135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.33667135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.298362181
Short name T634
Test name
Test status
Simulation time 247940529 ps
CPU time 5.78 seconds
Started Mar 19 01:05:04 PM PDT 24
Finished Mar 19 01:05:10 PM PDT 24
Peak memory 223864 kb
Host smart-4a543287-6792-4ab0-beab-acbc8525ee92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=298362181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.298362181 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.299187363
Short name T435
Test name
Test status
Simulation time 2603590970 ps
CPU time 16.85 seconds
Started Mar 19 01:05:03 PM PDT 24
Finished Mar 19 01:05:20 PM PDT 24
Peak memory 220200 kb
Host smart-283f7699-8fda-45e9-8dc5-9f5ec84e1825
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=299187363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.299187363 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.3361238353
Short name T740
Test name
Test status
Simulation time 9357347985 ps
CPU time 137.04 seconds
Started Mar 19 01:05:00 PM PDT 24
Finished Mar 19 01:07:18 PM PDT 24
Peak memory 233348 kb
Host smart-8b3298e3-5117-4f2c-a456-ff534feb0290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361238353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3361238353 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.4065306935
Short name T854
Test name
Test status
Simulation time 23185494824 ps
CPU time 248.94 seconds
Started Mar 19 01:05:04 PM PDT 24
Finished Mar 19 01:09:13 PM PDT 24
Peak memory 251480 kb
Host smart-20c3d611-cd22-48b4-87b8-16c9327530e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065306935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.4065306935 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.447676710
Short name T25
Test name
Test status
Simulation time 466772106 ps
CPU time 2.58 seconds
Started Mar 19 01:05:01 PM PDT 24
Finished Mar 19 01:05:04 PM PDT 24
Peak memory 207104 kb
Host smart-4f4c013a-5ede-473d-a06f-8caf089eb7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447676710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.447676710 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.2222292240
Short name T59
Test name
Test status
Simulation time 34320398 ps
CPU time 1.22 seconds
Started Mar 19 01:05:03 PM PDT 24
Finished Mar 19 01:05:04 PM PDT 24
Peak memory 215848 kb
Host smart-a63d6bce-65a3-4afe-933d-71f8d8408f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222292240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.2222292240 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.3392164048
Short name T690
Test name
Test status
Simulation time 532550640236 ps
CPU time 1182.41 seconds
Started Mar 19 01:05:01 PM PDT 24
Finished Mar 19 01:24:44 PM PDT 24
Peak memory 330092 kb
Host smart-d9d49360-c1b3-457e-b451-5fdce24060be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392164048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.3392164048 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.2655370360
Short name T1080
Test name
Test status
Simulation time 2539832190 ps
CPU time 15.35 seconds
Started Mar 19 01:05:05 PM PDT 24
Finished Mar 19 01:05:21 PM PDT 24
Peak memory 223084 kb
Host smart-ff306b70-e085-4e41-8cee-a7fe364ee525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655370360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.2655370360 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.1524071759
Short name T1045
Test name
Test status
Simulation time 602488903 ps
CPU time 31.25 seconds
Started Mar 19 01:05:04 PM PDT 24
Finished Mar 19 01:05:36 PM PDT 24
Peak memory 219712 kb
Host smart-964cf482-2474-4b3b-bf8a-92edb6807401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524071759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.1524071759 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.1144030996
Short name T765
Test name
Test status
Simulation time 1653731630 ps
CPU time 38.01 seconds
Started Mar 19 01:05:01 PM PDT 24
Finished Mar 19 01:05:39 PM PDT 24
Peak memory 232692 kb
Host smart-3325f302-3dda-4ad2-b228-37cf12f7c48a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1144030996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.1144030996 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.1497637263
Short name T204
Test name
Test status
Simulation time 1218226686 ps
CPU time 4.88 seconds
Started Mar 19 01:05:04 PM PDT 24
Finished Mar 19 01:05:09 PM PDT 24
Peak memory 215948 kb
Host smart-b0a1852e-d8a9-4d15-876e-0f13290f7333
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497637263 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.1497637263 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.4208425574
Short name T291
Test name
Test status
Simulation time 261778797 ps
CPU time 5.06 seconds
Started Mar 19 01:05:03 PM PDT 24
Finished Mar 19 01:05:08 PM PDT 24
Peak memory 216004 kb
Host smart-ec67d6f0-e4ba-4e59-9e99-14f940320c52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208425574 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.kmac_test_vectors_kmac_xof.4208425574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.1016528268
Short name T302
Test name
Test status
Simulation time 195099066540 ps
CPU time 1959.71 seconds
Started Mar 19 01:05:03 PM PDT 24
Finished Mar 19 01:37:43 PM PDT 24
Peak memory 379436 kb
Host smart-707ecbea-4d44-4649-b180-d5f6cd40d76c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1016528268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.1016528268 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.226757215
Short name T937
Test name
Test status
Simulation time 18034794455 ps
CPU time 1402.34 seconds
Started Mar 19 01:05:01 PM PDT 24
Finished Mar 19 01:28:24 PM PDT 24
Peak memory 364832 kb
Host smart-919cd9b0-cb85-40e4-9255-a0c5c0d4e541
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=226757215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.226757215 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.187052745
Short name T661
Test name
Test status
Simulation time 57286448681 ps
CPU time 1139.96 seconds
Started Mar 19 01:05:04 PM PDT 24
Finished Mar 19 01:24:05 PM PDT 24
Peak memory 337140 kb
Host smart-d6786636-9d43-4608-8093-1a969c6edc75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=187052745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.187052745 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.1726648935
Short name T812
Test name
Test status
Simulation time 181548803624 ps
CPU time 938.05 seconds
Started Mar 19 01:05:03 PM PDT 24
Finished Mar 19 01:20:41 PM PDT 24
Peak memory 292816 kb
Host smart-a649c7f4-c77d-445b-bbd1-157bbaf1a228
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1726648935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.1726648935 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.2702200070
Short name T423
Test name
Test status
Simulation time 51009932322 ps
CPU time 4144.55 seconds
Started Mar 19 01:05:01 PM PDT 24
Finished Mar 19 02:14:06 PM PDT 24
Peak memory 655388 kb
Host smart-035d5918-e55f-4969-aaf4-ff4462ddea78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2702200070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.2702200070 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.1550194206
Short name T763
Test name
Test status
Simulation time 221018704721 ps
CPU time 4509.53 seconds
Started Mar 19 01:05:01 PM PDT 24
Finished Mar 19 02:20:11 PM PDT 24
Peak memory 561224 kb
Host smart-06836314-09dc-489d-857d-7779e19d7167
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1550194206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.1550194206 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.866467377
Short name T284
Test name
Test status
Simulation time 205389019 ps
CPU time 0.75 seconds
Started Mar 19 01:05:21 PM PDT 24
Finished Mar 19 01:05:23 PM PDT 24
Peak memory 205292 kb
Host smart-2ce7bd11-9936-4645-b466-661c4c3f1761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866467377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.866467377 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.718045050
Short name T885
Test name
Test status
Simulation time 7313633087 ps
CPU time 197.85 seconds
Started Mar 19 01:05:15 PM PDT 24
Finished Mar 19 01:08:33 PM PDT 24
Peak memory 241488 kb
Host smart-350cccdf-234d-47c8-a458-23e0e8040248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718045050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.718045050 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.3487875067
Short name T82
Test name
Test status
Simulation time 24984098013 ps
CPU time 622.7 seconds
Started Mar 19 01:05:13 PM PDT 24
Finished Mar 19 01:15:36 PM PDT 24
Peak memory 231068 kb
Host smart-9f023a5a-6c35-4af3-9d20-5bbe431f74cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487875067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3487875067 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.3021233729
Short name T270
Test name
Test status
Simulation time 906365157 ps
CPU time 21.75 seconds
Started Mar 19 01:05:14 PM PDT 24
Finished Mar 19 01:05:36 PM PDT 24
Peak memory 232008 kb
Host smart-5c91bc1a-fad9-4537-80c7-430235a5da3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3021233729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3021233729 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.1521209510
Short name T215
Test name
Test status
Simulation time 3808524535 ps
CPU time 19.82 seconds
Started Mar 19 01:05:15 PM PDT 24
Finished Mar 19 01:05:35 PM PDT 24
Peak memory 223920 kb
Host smart-dfbda820-3908-4d60-9c0d-fb3e2e7132c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1521209510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.1521209510 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.3761043492
Short name T945
Test name
Test status
Simulation time 14146214745 ps
CPU time 184.65 seconds
Started Mar 19 01:05:14 PM PDT 24
Finished Mar 19 01:08:19 PM PDT 24
Peak memory 240272 kb
Host smart-99aa62cd-d9b9-4ae1-9249-28e24c5511a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761043492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.3761043492 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.2368394316
Short name T745
Test name
Test status
Simulation time 15755368049 ps
CPU time 339.52 seconds
Started Mar 19 01:05:14 PM PDT 24
Finished Mar 19 01:10:54 PM PDT 24
Peak memory 256936 kb
Host smart-05726e1e-ed13-43e3-97c9-76c44d660143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368394316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2368394316 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.1745916564
Short name T487
Test name
Test status
Simulation time 263465378 ps
CPU time 1.8 seconds
Started Mar 19 01:05:14 PM PDT 24
Finished Mar 19 01:05:17 PM PDT 24
Peak memory 207388 kb
Host smart-0222b627-8042-4e93-93a3-547a92bd29fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745916564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1745916564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.4139296934
Short name T339
Test name
Test status
Simulation time 473437534 ps
CPU time 1.27 seconds
Started Mar 19 01:05:16 PM PDT 24
Finished Mar 19 01:05:18 PM PDT 24
Peak memory 215884 kb
Host smart-c6969711-6a18-4096-ad2f-b23b62ecf15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139296934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.4139296934 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.1354012334
Short name T909
Test name
Test status
Simulation time 191373229036 ps
CPU time 1348.62 seconds
Started Mar 19 01:05:16 PM PDT 24
Finished Mar 19 01:27:45 PM PDT 24
Peak memory 346204 kb
Host smart-765424c4-05fd-41e2-9671-0bdc4ec82c23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354012334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.1354012334 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.3585615346
Short name T680
Test name
Test status
Simulation time 35443820528 ps
CPU time 260.17 seconds
Started Mar 19 01:05:22 PM PDT 24
Finished Mar 19 01:09:43 PM PDT 24
Peak memory 241080 kb
Host smart-801135e0-2a2f-4213-8ebd-9563b6d90145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585615346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.3585615346 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.2720285788
Short name T689
Test name
Test status
Simulation time 752767341 ps
CPU time 38.14 seconds
Started Mar 19 01:05:15 PM PDT 24
Finished Mar 19 01:05:53 PM PDT 24
Peak memory 219156 kb
Host smart-c9d2e606-b457-4dd6-94bc-139296f1a732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720285788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.2720285788 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.3078919809
Short name T178
Test name
Test status
Simulation time 478299023261 ps
CPU time 1261.34 seconds
Started Mar 19 01:05:13 PM PDT 24
Finished Mar 19 01:26:16 PM PDT 24
Peak memory 346512 kb
Host smart-737755af-420a-4a1f-bbe1-350ae8b91680
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3078919809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.3078919809 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.7356408
Short name T398
Test name
Test status
Simulation time 127680185 ps
CPU time 3.8 seconds
Started Mar 19 01:05:15 PM PDT 24
Finished Mar 19 01:05:19 PM PDT 24
Peak memory 215984 kb
Host smart-6fbf72c3-bb4d-4ac6-996b-7e7d3058d145
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7356408 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.kmac_test_vectors_kmac.7356408 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.1740843246
Short name T219
Test name
Test status
Simulation time 2159541485 ps
CPU time 5.43 seconds
Started Mar 19 01:05:15 PM PDT 24
Finished Mar 19 01:05:20 PM PDT 24
Peak memory 215996 kb
Host smart-0b916375-d57f-4b71-90ff-50e6f368f97e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740843246 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.kmac_test_vectors_kmac_xof.1740843246 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.1197436688
Short name T1029
Test name
Test status
Simulation time 35876543616 ps
CPU time 1452.44 seconds
Started Mar 19 01:05:15 PM PDT 24
Finished Mar 19 01:29:28 PM PDT 24
Peak memory 387872 kb
Host smart-0d49a8fd-efb2-46b7-a7fd-17d2f528df46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1197436688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.1197436688 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.1455000378
Short name T1067
Test name
Test status
Simulation time 18061501659 ps
CPU time 1495.59 seconds
Started Mar 19 01:05:21 PM PDT 24
Finished Mar 19 01:30:18 PM PDT 24
Peak memory 387088 kb
Host smart-e779ca2b-8c78-4ebc-9851-26ecfaa30814
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1455000378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.1455000378 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.46115203
Short name T551
Test name
Test status
Simulation time 196265797180 ps
CPU time 1284.73 seconds
Started Mar 19 01:05:12 PM PDT 24
Finished Mar 19 01:26:37 PM PDT 24
Peak memory 324452 kb
Host smart-3338117d-ec7d-4ee0-abfb-94b0f4e802e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=46115203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.46115203 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.4136682536
Short name T352
Test name
Test status
Simulation time 49379263444 ps
CPU time 789.18 seconds
Started Mar 19 01:05:14 PM PDT 24
Finished Mar 19 01:18:23 PM PDT 24
Peak memory 292812 kb
Host smart-8b0a3cd5-7739-4d22-966d-f96f1c7e754b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4136682536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.4136682536 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.989658919
Short name T263
Test name
Test status
Simulation time 60723553077 ps
CPU time 4109.4 seconds
Started Mar 19 01:05:14 PM PDT 24
Finished Mar 19 02:13:44 PM PDT 24
Peak memory 654940 kb
Host smart-bfe918df-b9b0-445b-8514-fc0c083c7284
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=989658919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.989658919 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.3941375766
Short name T80
Test name
Test status
Simulation time 317354565304 ps
CPU time 4485.24 seconds
Started Mar 19 01:05:13 PM PDT 24
Finished Mar 19 02:19:59 PM PDT 24
Peak memory 569920 kb
Host smart-500322e3-6a6b-48db-bd12-894bf062dfcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3941375766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.3941375766 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.4137172328
Short name T674
Test name
Test status
Simulation time 17191288 ps
CPU time 0.81 seconds
Started Mar 19 01:05:23 PM PDT 24
Finished Mar 19 01:05:24 PM PDT 24
Peak memory 205388 kb
Host smart-8ae92650-3af1-4e4f-9484-1f9124fd2ae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137172328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.4137172328 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.863209014
Short name T1037
Test name
Test status
Simulation time 12990795958 ps
CPU time 92.78 seconds
Started Mar 19 01:05:23 PM PDT 24
Finished Mar 19 01:06:56 PM PDT 24
Peak memory 228132 kb
Host smart-9062ddf1-eb4d-4b24-bd1e-104034f6ca76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863209014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.863209014 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.3031730800
Short name T876
Test name
Test status
Simulation time 104656856270 ps
CPU time 597.89 seconds
Started Mar 19 01:05:12 PM PDT 24
Finished Mar 19 01:15:11 PM PDT 24
Peak memory 231660 kb
Host smart-2d006835-1d7c-4201-a129-508368b266f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031730800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.3031730800 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.1720163147
Short name T472
Test name
Test status
Simulation time 845202567 ps
CPU time 16.37 seconds
Started Mar 19 01:05:20 PM PDT 24
Finished Mar 19 01:05:36 PM PDT 24
Peak memory 223896 kb
Host smart-bed0381b-8c97-48e1-affe-14fb0d832821
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1720163147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.1720163147 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.2100597897
Short name T592
Test name
Test status
Simulation time 1022852020 ps
CPU time 20.47 seconds
Started Mar 19 01:05:23 PM PDT 24
Finished Mar 19 01:05:44 PM PDT 24
Peak memory 218004 kb
Host smart-422850f8-f677-4584-b0f7-4a379d7e53bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2100597897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.2100597897 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.1046326725
Short name T962
Test name
Test status
Simulation time 6979900547 ps
CPU time 37.9 seconds
Started Mar 19 01:05:18 PM PDT 24
Finished Mar 19 01:05:57 PM PDT 24
Peak memory 222192 kb
Host smart-86d39a8e-1ab4-4c83-843d-82bdbba22dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046326725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.1046326725 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.2430049202
Short name T788
Test name
Test status
Simulation time 50059357776 ps
CPU time 338.95 seconds
Started Mar 19 01:05:21 PM PDT 24
Finished Mar 19 01:11:00 PM PDT 24
Peak memory 256824 kb
Host smart-08d86e20-807c-4a01-8106-71702525e537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430049202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.2430049202 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.2353212123
Short name T65
Test name
Test status
Simulation time 693541290 ps
CPU time 3.88 seconds
Started Mar 19 01:05:20 PM PDT 24
Finished Mar 19 01:05:24 PM PDT 24
Peak memory 207288 kb
Host smart-013dbcaa-1af4-450f-8517-b24d20cc5f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353212123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.2353212123 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.1007560235
Short name T54
Test name
Test status
Simulation time 1440141201 ps
CPU time 7.28 seconds
Started Mar 19 01:05:27 PM PDT 24
Finished Mar 19 01:05:35 PM PDT 24
Peak memory 224180 kb
Host smart-c9c65946-f126-4e80-8304-b7a886160d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007560235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.1007560235 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.2725933525
Short name T1084
Test name
Test status
Simulation time 11237610361 ps
CPU time 498.72 seconds
Started Mar 19 01:05:15 PM PDT 24
Finished Mar 19 01:13:34 PM PDT 24
Peak memory 273940 kb
Host smart-ca9134b8-1d82-45f0-9b58-5492bca4bb0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725933525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.2725933525 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.2626896972
Short name T610
Test name
Test status
Simulation time 4994645093 ps
CPU time 63.89 seconds
Started Mar 19 01:05:14 PM PDT 24
Finished Mar 19 01:06:18 PM PDT 24
Peak memory 224232 kb
Host smart-051d205d-7c98-480e-9db8-ddf1b4fb5af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626896972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2626896972 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.851501415
Short name T19
Test name
Test status
Simulation time 210025521 ps
CPU time 11.4 seconds
Started Mar 19 01:05:13 PM PDT 24
Finished Mar 19 01:05:25 PM PDT 24
Peak memory 219272 kb
Host smart-8c1e0cfc-74ad-4af0-a0a4-584efd08d6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851501415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.851501415 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.1757588027
Short name T417
Test name
Test status
Simulation time 202623301 ps
CPU time 4.2 seconds
Started Mar 19 01:05:19 PM PDT 24
Finished Mar 19 01:05:24 PM PDT 24
Peak memory 215932 kb
Host smart-c89fa4ca-0704-4dda-9ed6-4b2095cbe028
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757588027 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.kmac_test_vectors_kmac.1757588027 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.186449818
Short name T465
Test name
Test status
Simulation time 641659392 ps
CPU time 4.74 seconds
Started Mar 19 01:05:22 PM PDT 24
Finished Mar 19 01:05:27 PM PDT 24
Peak memory 215832 kb
Host smart-0812708c-8136-4416-a6d5-0648b5cf5a08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186449818 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.kmac_test_vectors_kmac_xof.186449818 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.4171404310
Short name T656
Test name
Test status
Simulation time 67729347904 ps
CPU time 1776.43 seconds
Started Mar 19 01:05:21 PM PDT 24
Finished Mar 19 01:34:58 PM PDT 24
Peak memory 388980 kb
Host smart-48de4eeb-e65d-49f8-9d24-f8a6b6004c1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4171404310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.4171404310 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.3877182057
Short name T841
Test name
Test status
Simulation time 74598361022 ps
CPU time 1529.61 seconds
Started Mar 19 01:05:13 PM PDT 24
Finished Mar 19 01:30:43 PM PDT 24
Peak memory 377472 kb
Host smart-6b354d4c-2364-4c44-8ddf-12cb74915d5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3877182057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.3877182057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.1070176038
Short name T808
Test name
Test status
Simulation time 94574737618 ps
CPU time 1312.58 seconds
Started Mar 19 01:05:13 PM PDT 24
Finished Mar 19 01:27:06 PM PDT 24
Peak memory 336876 kb
Host smart-82163b4e-12e1-4539-8eaf-bacc7d12b89f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1070176038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.1070176038 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.53841231
Short name T498
Test name
Test status
Simulation time 32411055629 ps
CPU time 895.32 seconds
Started Mar 19 01:05:13 PM PDT 24
Finished Mar 19 01:20:09 PM PDT 24
Peak memory 293528 kb
Host smart-91a0bbc4-c128-445e-8de6-9d13ef889330
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=53841231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.53841231 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.3353763745
Short name T334
Test name
Test status
Simulation time 259493091889 ps
CPU time 5400.84 seconds
Started Mar 19 01:05:17 PM PDT 24
Finished Mar 19 02:35:18 PM PDT 24
Peak memory 660864 kb
Host smart-620f4ca3-a4f9-4f42-8834-30ddb2183347
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3353763745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.3353763745 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.2603816194
Short name T292
Test name
Test status
Simulation time 239405864344 ps
CPU time 3557.59 seconds
Started Mar 19 01:05:20 PM PDT 24
Finished Mar 19 02:04:38 PM PDT 24
Peak memory 557784 kb
Host smart-798825c4-bb9a-49e6-8552-ee5ddc5d4539
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2603816194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.2603816194 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.2186681625
Short name T223
Test name
Test status
Simulation time 37066291 ps
CPU time 0.84 seconds
Started Mar 19 01:05:23 PM PDT 24
Finished Mar 19 01:05:24 PM PDT 24
Peak memory 205304 kb
Host smart-58ec716b-6665-4cbc-9026-de8e719681f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186681625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.2186681625 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.3380781436
Short name T641
Test name
Test status
Simulation time 14409094389 ps
CPU time 304.04 seconds
Started Mar 19 01:05:22 PM PDT 24
Finished Mar 19 01:10:26 PM PDT 24
Peak memory 247704 kb
Host smart-2f511e5f-68b8-4f9d-9b6c-da43b8efba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380781436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.3380781436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.1285586372
Short name T814
Test name
Test status
Simulation time 26303998081 ps
CPU time 389.69 seconds
Started Mar 19 01:05:19 PM PDT 24
Finished Mar 19 01:11:49 PM PDT 24
Peak memory 230512 kb
Host smart-6731011f-e1dd-4d9f-97c0-a995bb5af7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285586372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.1285586372 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.330656192
Short name T359
Test name
Test status
Simulation time 140219570 ps
CPU time 9.96 seconds
Started Mar 19 01:05:23 PM PDT 24
Finished Mar 19 01:05:33 PM PDT 24
Peak memory 222856 kb
Host smart-0bab38ff-6f22-479b-a851-9019ac78e21e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=330656192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.330656192 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.2809972849
Short name T534
Test name
Test status
Simulation time 1385493808 ps
CPU time 26.66 seconds
Started Mar 19 01:05:22 PM PDT 24
Finished Mar 19 01:05:49 PM PDT 24
Peak memory 223924 kb
Host smart-be9b706a-1afa-4270-8943-c7940b54f42f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2809972849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2809972849 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.3484329711
Short name T917
Test name
Test status
Simulation time 10922096902 ps
CPU time 216.57 seconds
Started Mar 19 01:05:23 PM PDT 24
Finished Mar 19 01:09:00 PM PDT 24
Peak memory 240152 kb
Host smart-a0144f5e-dfef-48c0-81f1-1e188fa4207b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484329711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3484329711 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.700789545
Short name T999
Test name
Test status
Simulation time 43566205539 ps
CPU time 180.12 seconds
Started Mar 19 01:05:21 PM PDT 24
Finished Mar 19 01:08:22 PM PDT 24
Peak memory 248676 kb
Host smart-18db485a-18fc-4585-a657-526f3ded827e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700789545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.700789545 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.765596671
Short name T1072
Test name
Test status
Simulation time 646167532 ps
CPU time 3.16 seconds
Started Mar 19 01:05:19 PM PDT 24
Finished Mar 19 01:05:23 PM PDT 24
Peak memory 207368 kb
Host smart-6c162f38-b32a-40c8-83c8-64136e9adb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765596671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.765596671 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.3400850337
Short name T7
Test name
Test status
Simulation time 86447498 ps
CPU time 1.3 seconds
Started Mar 19 01:05:21 PM PDT 24
Finished Mar 19 01:05:23 PM PDT 24
Peak memory 215824 kb
Host smart-82c2c133-6ad8-47b7-bb07-429462c121ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400850337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.3400850337 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.3521589322
Short name T552
Test name
Test status
Simulation time 214350256923 ps
CPU time 2217.75 seconds
Started Mar 19 01:05:21 PM PDT 24
Finished Mar 19 01:42:19 PM PDT 24
Peak memory 427100 kb
Host smart-6d659dac-1104-4316-b07a-038e069c8051
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521589322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.3521589322 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.3975277722
Short name T414
Test name
Test status
Simulation time 19872243864 ps
CPU time 412.88 seconds
Started Mar 19 01:05:21 PM PDT 24
Finished Mar 19 01:12:15 PM PDT 24
Peak memory 251484 kb
Host smart-b480ac88-c625-4354-974a-e4ccd3410677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975277722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3975277722 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.2469426351
Short name T839
Test name
Test status
Simulation time 6777388919 ps
CPU time 28.31 seconds
Started Mar 19 01:05:22 PM PDT 24
Finished Mar 19 01:05:51 PM PDT 24
Peak memory 219156 kb
Host smart-eef0c0fd-753d-4858-bbd9-578e207f1060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469426351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2469426351 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.2229758729
Short name T85
Test name
Test status
Simulation time 43650637719 ps
CPU time 243.06 seconds
Started Mar 19 01:05:21 PM PDT 24
Finished Mar 19 01:09:25 PM PDT 24
Peak memory 244524 kb
Host smart-12246603-ef16-4b97-a05b-71ecbc5df42a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2229758729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.2229758729 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.652884597
Short name T789
Test name
Test status
Simulation time 1007532045 ps
CPU time 4.05 seconds
Started Mar 19 01:05:21 PM PDT 24
Finished Mar 19 01:05:26 PM PDT 24
Peak memory 215892 kb
Host smart-645a6e59-5ced-4b92-9855-3d5651c78bda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652884597 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.kmac_test_vectors_kmac.652884597 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.885683684
Short name T326
Test name
Test status
Simulation time 125416788 ps
CPU time 3.97 seconds
Started Mar 19 01:05:27 PM PDT 24
Finished Mar 19 01:05:32 PM PDT 24
Peak memory 215932 kb
Host smart-49047c01-7878-458c-8188-453eda39a682
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885683684 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.kmac_test_vectors_kmac_xof.885683684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.397222183
Short name T234
Test name
Test status
Simulation time 68109057198 ps
CPU time 1942.15 seconds
Started Mar 19 01:05:27 PM PDT 24
Finished Mar 19 01:37:50 PM PDT 24
Peak memory 399468 kb
Host smart-060a6a9d-6b28-4f6c-9229-7c9914227a7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=397222183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.397222183 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.239854521
Short name T330
Test name
Test status
Simulation time 132667312469 ps
CPU time 1656.51 seconds
Started Mar 19 01:05:20 PM PDT 24
Finished Mar 19 01:32:57 PM PDT 24
Peak memory 373284 kb
Host smart-760a4abb-0b49-4b02-8b30-42a0b4cf455d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=239854521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.239854521 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.3160941220
Short name T643
Test name
Test status
Simulation time 54263437317 ps
CPU time 1135.71 seconds
Started Mar 19 01:05:21 PM PDT 24
Finished Mar 19 01:24:17 PM PDT 24
Peak memory 334168 kb
Host smart-f3240548-f49e-478b-997e-2995009b7a79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3160941220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.3160941220 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.1765500408
Short name T1044
Test name
Test status
Simulation time 168427200239 ps
CPU time 969.28 seconds
Started Mar 19 01:05:19 PM PDT 24
Finished Mar 19 01:21:29 PM PDT 24
Peak memory 293856 kb
Host smart-689d036c-b16f-4e2d-9b93-cecc090ec30b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1765500408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.1765500408 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.3252187572
Short name T758
Test name
Test status
Simulation time 1420234271637 ps
CPU time 4461.84 seconds
Started Mar 19 01:05:22 PM PDT 24
Finished Mar 19 02:19:45 PM PDT 24
Peak memory 641340 kb
Host smart-8ccd9de4-59e0-4c3b-afb8-83afd3c14b7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3252187572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.3252187572 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.1685695666
Short name T672
Test name
Test status
Simulation time 152343771931 ps
CPU time 4365.13 seconds
Started Mar 19 01:05:27 PM PDT 24
Finished Mar 19 02:18:13 PM PDT 24
Peak memory 566240 kb
Host smart-f7c32f85-557a-42e2-93c7-2a55daec8d3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1685695666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.1685695666 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.3283769546
Short name T49
Test name
Test status
Simulation time 48131932 ps
CPU time 0.8 seconds
Started Mar 19 01:05:44 PM PDT 24
Finished Mar 19 01:05:46 PM PDT 24
Peak memory 205308 kb
Host smart-9f7557e1-dfe7-4540-ae4f-17994de140e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283769546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.3283769546 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.3701097565
Short name T921
Test name
Test status
Simulation time 29183406949 ps
CPU time 220.8 seconds
Started Mar 19 01:05:36 PM PDT 24
Finished Mar 19 01:09:17 PM PDT 24
Peak memory 240348 kb
Host smart-316f6383-3970-40ea-99e7-6352e045de98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701097565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3701097565 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.2774366673
Short name T603
Test name
Test status
Simulation time 52414622113 ps
CPU time 466.58 seconds
Started Mar 19 01:05:31 PM PDT 24
Finished Mar 19 01:13:18 PM PDT 24
Peak memory 229392 kb
Host smart-367f4152-b70e-42f0-b10d-ec5be64b2b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774366673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.2774366673 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.3495724751
Short name T774
Test name
Test status
Simulation time 3706930921 ps
CPU time 40.37 seconds
Started Mar 19 01:05:34 PM PDT 24
Finished Mar 19 01:06:15 PM PDT 24
Peak memory 223888 kb
Host smart-28d000cf-2647-45b6-bbc3-982a6f14a9f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3495724751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3495724751 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.1433924302
Short name T544
Test name
Test status
Simulation time 199708875 ps
CPU time 13.19 seconds
Started Mar 19 01:05:32 PM PDT 24
Finished Mar 19 01:05:45 PM PDT 24
Peak memory 216680 kb
Host smart-0fae7d0f-a48f-43c4-a3e3-c6e39704d1a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1433924302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.1433924302 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.2195939957
Short name T884
Test name
Test status
Simulation time 13028187942 ps
CPU time 254.38 seconds
Started Mar 19 01:05:33 PM PDT 24
Finished Mar 19 01:09:47 PM PDT 24
Peak memory 242676 kb
Host smart-66323e9d-8653-43a2-837c-5633245b15be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195939957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.2195939957 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.3522165001
Short name T657
Test name
Test status
Simulation time 330763437 ps
CPU time 6.3 seconds
Started Mar 19 01:05:33 PM PDT 24
Finished Mar 19 01:05:40 PM PDT 24
Peak memory 224072 kb
Host smart-ee98862e-4cec-4e04-9726-77bfed0739e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522165001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.3522165001 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.1439634374
Short name T903
Test name
Test status
Simulation time 3739187169 ps
CPU time 6.18 seconds
Started Mar 19 01:05:35 PM PDT 24
Finished Mar 19 01:05:43 PM PDT 24
Peak memory 207552 kb
Host smart-f1d5231f-57d5-46dc-8f11-127bb6111532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439634374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.1439634374 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.4109185986
Short name T345
Test name
Test status
Simulation time 625461887 ps
CPU time 1.28 seconds
Started Mar 19 01:05:34 PM PDT 24
Finished Mar 19 01:05:36 PM PDT 24
Peak memory 220028 kb
Host smart-b11157f0-c575-4c7b-b04a-3adf1dd3b21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109185986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.4109185986 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.3736839814
Short name T667
Test name
Test status
Simulation time 148851896720 ps
CPU time 2815.31 seconds
Started Mar 19 01:05:20 PM PDT 24
Finished Mar 19 01:52:16 PM PDT 24
Peak memory 480136 kb
Host smart-c3990c71-73ef-4545-9af9-8dd39b984cb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736839814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.3736839814 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.2664739456
Short name T392
Test name
Test status
Simulation time 8964330451 ps
CPU time 239.35 seconds
Started Mar 19 01:05:19 PM PDT 24
Finished Mar 19 01:09:19 PM PDT 24
Peak memory 240884 kb
Host smart-1002c98a-d03d-448d-832b-f7be904cf827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664739456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2664739456 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.3982543513
Short name T955
Test name
Test status
Simulation time 667012271 ps
CPU time 25.24 seconds
Started Mar 19 01:05:22 PM PDT 24
Finished Mar 19 01:05:48 PM PDT 24
Peak memory 218500 kb
Host smart-d3fdaf76-6ce5-4cd7-8d08-86b56a51966d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982543513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.3982543513 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.3802311385
Short name T427
Test name
Test status
Simulation time 4619434511 ps
CPU time 115.14 seconds
Started Mar 19 01:05:33 PM PDT 24
Finished Mar 19 01:07:29 PM PDT 24
Peak memory 243232 kb
Host smart-37634014-f40f-47cb-8bf7-ff8ccb609751
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3802311385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.3802311385 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.2656471104
Short name T806
Test name
Test status
Simulation time 236706099 ps
CPU time 3.96 seconds
Started Mar 19 01:05:32 PM PDT 24
Finished Mar 19 01:05:36 PM PDT 24
Peak memory 207820 kb
Host smart-63f8fa8f-29fd-4e29-9bd0-67da7b52adad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656471104 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.kmac_test_vectors_kmac.2656471104 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.1157504342
Short name T348
Test name
Test status
Simulation time 927166541 ps
CPU time 5.68 seconds
Started Mar 19 01:05:34 PM PDT 24
Finished Mar 19 01:05:40 PM PDT 24
Peak memory 209008 kb
Host smart-161b0c65-8b23-49ba-b2eb-45b90b9d07ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157504342 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.1157504342 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.1526782589
Short name T995
Test name
Test status
Simulation time 528139218123 ps
CPU time 2003.27 seconds
Started Mar 19 01:05:33 PM PDT 24
Finished Mar 19 01:38:57 PM PDT 24
Peak memory 377188 kb
Host smart-941783e7-a436-4109-a95d-66426a83b325
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1526782589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.1526782589 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.1162043695
Short name T971
Test name
Test status
Simulation time 73386822922 ps
CPU time 1451.73 seconds
Started Mar 19 01:05:32 PM PDT 24
Finished Mar 19 01:29:44 PM PDT 24
Peak memory 371880 kb
Host smart-6a47d0d5-e8b6-495b-a29b-84e01c9d82e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1162043695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.1162043695 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.2489871130
Short name T298
Test name
Test status
Simulation time 28875705448 ps
CPU time 1145.54 seconds
Started Mar 19 01:05:34 PM PDT 24
Finished Mar 19 01:24:40 PM PDT 24
Peak memory 340184 kb
Host smart-0300bc68-eaa2-428b-8c65-d97e423a7c16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2489871130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.2489871130 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.1126828009
Short name T701
Test name
Test status
Simulation time 10154642912 ps
CPU time 776.86 seconds
Started Mar 19 01:05:31 PM PDT 24
Finished Mar 19 01:18:28 PM PDT 24
Peak memory 293836 kb
Host smart-2bbb9d3e-1964-4b6e-9d2d-7f9b5d852720
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1126828009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.1126828009 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.3519514150
Short name T233
Test name
Test status
Simulation time 497962221361 ps
CPU time 5205.09 seconds
Started Mar 19 01:05:31 PM PDT 24
Finished Mar 19 02:32:17 PM PDT 24
Peak memory 663172 kb
Host smart-97c61b7f-d44b-4c19-894c-ae29fb3ac81e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3519514150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.3519514150 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.2872151200
Short name T677
Test name
Test status
Simulation time 1223115622812 ps
CPU time 4231.21 seconds
Started Mar 19 01:05:32 PM PDT 24
Finished Mar 19 02:16:04 PM PDT 24
Peak memory 570840 kb
Host smart-6f77f02f-d2a2-4c2a-abb6-603f2e42ae76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2872151200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.2872151200 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.290393664
Short name T217
Test name
Test status
Simulation time 58172938 ps
CPU time 0.77 seconds
Started Mar 19 01:03:48 PM PDT 24
Finished Mar 19 01:03:50 PM PDT 24
Peak memory 205420 kb
Host smart-9b872a91-608d-4f62-9eeb-6e59c4832a5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290393664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.290393664 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.1735745945
Short name T666
Test name
Test status
Simulation time 44592809452 ps
CPU time 262.42 seconds
Started Mar 19 01:03:41 PM PDT 24
Finished Mar 19 01:08:04 PM PDT 24
Peak memory 241780 kb
Host smart-37050a7a-1fa7-4c12-96c3-568f8e0c1830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735745945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1735745945 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.1491099078
Short name T344
Test name
Test status
Simulation time 12830845940 ps
CPU time 273.72 seconds
Started Mar 19 01:04:01 PM PDT 24
Finished Mar 19 01:08:35 PM PDT 24
Peak memory 245652 kb
Host smart-e39485de-5b6c-4d9a-936e-85bf2a460b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491099078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.1491099078 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.3560183495
Short name T177
Test name
Test status
Simulation time 27688164646 ps
CPU time 587.41 seconds
Started Mar 19 01:03:40 PM PDT 24
Finished Mar 19 01:13:29 PM PDT 24
Peak memory 230504 kb
Host smart-28921e44-f12a-45b9-b8e2-ab934c2ef97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560183495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3560183495 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.4012168323
Short name T564
Test name
Test status
Simulation time 109579269 ps
CPU time 4.28 seconds
Started Mar 19 01:03:52 PM PDT 24
Finished Mar 19 01:03:57 PM PDT 24
Peak memory 220236 kb
Host smart-e4227386-1a5f-46a6-8494-5c4208bb925f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4012168323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.4012168323 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.2730233725
Short name T952
Test name
Test status
Simulation time 358637626 ps
CPU time 23.57 seconds
Started Mar 19 01:03:51 PM PDT 24
Finished Mar 19 01:04:16 PM PDT 24
Peak memory 223896 kb
Host smart-f14e4867-79cc-4dc4-ad76-e572c852c456
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2730233725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.2730233725 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.328599808
Short name T1047
Test name
Test status
Simulation time 11012903341 ps
CPU time 30.22 seconds
Started Mar 19 01:03:45 PM PDT 24
Finished Mar 19 01:04:17 PM PDT 24
Peak memory 216044 kb
Host smart-95983d5c-4e04-47ef-8480-4ca013037542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328599808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.328599808 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.1836943067
Short name T1063
Test name
Test status
Simulation time 55380233553 ps
CPU time 242.19 seconds
Started Mar 19 01:03:46 PM PDT 24
Finished Mar 19 01:07:49 PM PDT 24
Peak memory 238500 kb
Host smart-f4045c8f-6771-429f-9030-8c6fea60cbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836943067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.1836943067 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.2654853854
Short name T503
Test name
Test status
Simulation time 10771172364 ps
CPU time 195.85 seconds
Started Mar 19 01:03:52 PM PDT 24
Finished Mar 19 01:07:08 PM PDT 24
Peak memory 256756 kb
Host smart-ea945108-df12-48f7-ac1e-ec2ce2c10e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654853854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.2654853854 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.1341406626
Short name T753
Test name
Test status
Simulation time 4013983484 ps
CPU time 6.44 seconds
Started Mar 19 01:03:49 PM PDT 24
Finished Mar 19 01:03:56 PM PDT 24
Peak memory 207668 kb
Host smart-c75a8a8c-e944-4792-90cd-d4002f019824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341406626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1341406626 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.3362328947
Short name T486
Test name
Test status
Simulation time 378437987 ps
CPU time 7.31 seconds
Started Mar 19 01:03:48 PM PDT 24
Finished Mar 19 01:03:56 PM PDT 24
Peak memory 224168 kb
Host smart-f131ea9f-597c-4f9e-afe3-dcca25897de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362328947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.3362328947 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.2035971132
Short name T283
Test name
Test status
Simulation time 25222868095 ps
CPU time 2063.69 seconds
Started Mar 19 01:03:59 PM PDT 24
Finished Mar 19 01:38:23 PM PDT 24
Peak memory 451436 kb
Host smart-93aaec52-93f3-4d02-a4d9-4f5ad7400d52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035971132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.2035971132 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.2014812601
Short name T88
Test name
Test status
Simulation time 17757316642 ps
CPU time 249.2 seconds
Started Mar 19 01:03:49 PM PDT 24
Finished Mar 19 01:07:59 PM PDT 24
Peak memory 242964 kb
Host smart-8a5516d5-7915-44c6-b982-be877543d371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014812601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.2014812601 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.2303535402
Short name T72
Test name
Test status
Simulation time 12463164488 ps
CPU time 53.44 seconds
Started Mar 19 01:03:52 PM PDT 24
Finished Mar 19 01:04:46 PM PDT 24
Peak memory 256028 kb
Host smart-f245d570-a007-411a-9cef-aad3f2d2653d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303535402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.2303535402 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.2953963205
Short name T563
Test name
Test status
Simulation time 6251111356 ps
CPU time 162.49 seconds
Started Mar 19 01:03:41 PM PDT 24
Finished Mar 19 01:06:24 PM PDT 24
Peak memory 233652 kb
Host smart-eef7d6ab-b494-438a-ad8c-b8242afa6444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953963205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.2953963205 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.2941320676
Short name T205
Test name
Test status
Simulation time 3321415774 ps
CPU time 28.05 seconds
Started Mar 19 01:03:43 PM PDT 24
Finished Mar 19 01:04:11 PM PDT 24
Peak memory 219436 kb
Host smart-fe640775-5ed7-4980-a43a-6b28fdc23cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941320676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.2941320676 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.1537815079
Short name T797
Test name
Test status
Simulation time 262328024 ps
CPU time 4.23 seconds
Started Mar 19 01:03:43 PM PDT 24
Finished Mar 19 01:03:47 PM PDT 24
Peak memory 215892 kb
Host smart-e9d85b2c-bc86-4c0a-a32f-0002e27e756e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537815079 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.1537815079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.862114874
Short name T589
Test name
Test status
Simulation time 750563905 ps
CPU time 4.74 seconds
Started Mar 19 01:03:43 PM PDT 24
Finished Mar 19 01:03:48 PM PDT 24
Peak memory 208992 kb
Host smart-02afd7a8-68d3-45ff-892d-b9dbc36304e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862114874 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.kmac_test_vectors_kmac_xof.862114874 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.2005590849
Short name T598
Test name
Test status
Simulation time 888017961494 ps
CPU time 2127.21 seconds
Started Mar 19 01:03:43 PM PDT 24
Finished Mar 19 01:39:11 PM PDT 24
Peak memory 393972 kb
Host smart-6c45231b-9085-4da2-a179-a3ed48267ba0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2005590849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.2005590849 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.609756111
Short name T390
Test name
Test status
Simulation time 75186939866 ps
CPU time 1384.68 seconds
Started Mar 19 01:03:40 PM PDT 24
Finished Mar 19 01:26:46 PM PDT 24
Peak memory 365072 kb
Host smart-c5cfb8b6-f861-4fcd-8a29-7656b504b34d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=609756111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.609756111 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.740128442
Short name T194
Test name
Test status
Simulation time 13862892960 ps
CPU time 1112.46 seconds
Started Mar 19 01:03:40 PM PDT 24
Finished Mar 19 01:22:14 PM PDT 24
Peak memory 330840 kb
Host smart-7e89b82f-1a9a-43be-ba63-d00e7c1e9c78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=740128442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.740128442 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.3210806229
Short name T449
Test name
Test status
Simulation time 410753046316 ps
CPU time 998.82 seconds
Started Mar 19 01:03:56 PM PDT 24
Finished Mar 19 01:20:35 PM PDT 24
Peak memory 296680 kb
Host smart-cbdc11f0-90bc-4e79-b18f-cc00e74b2c58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3210806229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.3210806229 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.242777467
Short name T255
Test name
Test status
Simulation time 218369862556 ps
CPU time 4208.02 seconds
Started Mar 19 01:03:44 PM PDT 24
Finished Mar 19 02:13:52 PM PDT 24
Peak memory 569064 kb
Host smart-9bcb5256-fb0c-4586-bf5d-26deb6e422e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=242777467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.242777467 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.364219096
Short name T335
Test name
Test status
Simulation time 17521991 ps
CPU time 0.74 seconds
Started Mar 19 01:05:45 PM PDT 24
Finished Mar 19 01:05:46 PM PDT 24
Peak memory 205336 kb
Host smart-d931bdac-91bc-4c3c-a10b-177904dea197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364219096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.364219096 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.1903754052
Short name T739
Test name
Test status
Simulation time 63288407665 ps
CPU time 295.46 seconds
Started Mar 19 01:05:48 PM PDT 24
Finished Mar 19 01:10:44 PM PDT 24
Peak memory 243488 kb
Host smart-267a4361-c5ca-4efd-86d5-49fa22f057b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903754052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.1903754052 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.931248366
Short name T1075
Test name
Test status
Simulation time 76130861741 ps
CPU time 547.28 seconds
Started Mar 19 01:05:43 PM PDT 24
Finished Mar 19 01:14:51 PM PDT 24
Peak memory 229924 kb
Host smart-3aaa05cc-fac8-47f5-a78d-78f08ac08b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931248366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.931248366 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.2580883440
Short name T305
Test name
Test status
Simulation time 3277583647 ps
CPU time 20.83 seconds
Started Mar 19 01:05:42 PM PDT 24
Finished Mar 19 01:06:03 PM PDT 24
Peak memory 224228 kb
Host smart-c1305cf7-855d-4669-b6ea-c792258249d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580883440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2580883440 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.1295784586
Short name T972
Test name
Test status
Simulation time 413312243 ps
CPU time 28.4 seconds
Started Mar 19 01:05:46 PM PDT 24
Finished Mar 19 01:06:15 PM PDT 24
Peak memory 238440 kb
Host smart-66fc74f1-fd7e-4d9e-824e-db4563c84c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295784586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1295784586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.2390814946
Short name T719
Test name
Test status
Simulation time 2017620886 ps
CPU time 4.9 seconds
Started Mar 19 01:05:43 PM PDT 24
Finished Mar 19 01:05:48 PM PDT 24
Peak memory 207480 kb
Host smart-8e6cd908-6a40-47bf-8bae-e701c809dd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390814946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.2390814946 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.3886945220
Short name T834
Test name
Test status
Simulation time 82800954 ps
CPU time 1.4 seconds
Started Mar 19 01:05:43 PM PDT 24
Finished Mar 19 01:05:45 PM PDT 24
Peak memory 216932 kb
Host smart-c13e2b41-f948-46a1-9d90-39c64ca5425e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886945220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.3886945220 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.1537671772
Short name T246
Test name
Test status
Simulation time 8772921303 ps
CPU time 265.89 seconds
Started Mar 19 01:05:42 PM PDT 24
Finished Mar 19 01:10:08 PM PDT 24
Peak memory 246300 kb
Host smart-75c9b403-e537-41d8-8ab8-38f97a72ae57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537671772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.1537671772 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.119608964
Short name T659
Test name
Test status
Simulation time 1402585135 ps
CPU time 108.8 seconds
Started Mar 19 01:05:43 PM PDT 24
Finished Mar 19 01:07:33 PM PDT 24
Peak memory 230616 kb
Host smart-1713bc64-f327-488a-b89f-8152c7090047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119608964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.119608964 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.596355306
Short name T609
Test name
Test status
Simulation time 1528195040 ps
CPU time 23.74 seconds
Started Mar 19 01:05:42 PM PDT 24
Finished Mar 19 01:06:06 PM PDT 24
Peak memory 217388 kb
Host smart-845736ff-be5e-4a41-9039-1fe5cc5435a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596355306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.596355306 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.174883796
Short name T548
Test name
Test status
Simulation time 44483141255 ps
CPU time 259.3 seconds
Started Mar 19 01:05:42 PM PDT 24
Finished Mar 19 01:10:02 PM PDT 24
Peak memory 273084 kb
Host smart-90c5218d-aff2-4128-9374-db155a00c816
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=174883796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.174883796 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.3089636247
Short name T360
Test name
Test status
Simulation time 688941045 ps
CPU time 4.75 seconds
Started Mar 19 01:05:47 PM PDT 24
Finished Mar 19 01:05:52 PM PDT 24
Peak memory 215980 kb
Host smart-7c9a0f5e-9e4e-47bb-bdb6-cb1212cbe2c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089636247 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.3089636247 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.2126699636
Short name T530
Test name
Test status
Simulation time 857176199 ps
CPU time 4.29 seconds
Started Mar 19 01:05:45 PM PDT 24
Finished Mar 19 01:05:49 PM PDT 24
Peak memory 215928 kb
Host smart-4cc8712a-338e-454b-aeb5-4675cc1b0a0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126699636 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.kmac_test_vectors_kmac_xof.2126699636 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.2682370207
Short name T768
Test name
Test status
Simulation time 1663566309516 ps
CPU time 2061.43 seconds
Started Mar 19 01:05:43 PM PDT 24
Finished Mar 19 01:40:05 PM PDT 24
Peak memory 402680 kb
Host smart-feac3346-d0c3-4d87-9c66-de473e1c5466
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2682370207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.2682370207 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.3230998758
Short name T276
Test name
Test status
Simulation time 70248843449 ps
CPU time 1307.79 seconds
Started Mar 19 01:05:45 PM PDT 24
Finished Mar 19 01:27:34 PM PDT 24
Peak memory 370248 kb
Host smart-905e6f18-3edb-4639-b33e-f2f607cdad03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3230998758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.3230998758 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.1647064099
Short name T725
Test name
Test status
Simulation time 28004617695 ps
CPU time 1083.89 seconds
Started Mar 19 01:05:44 PM PDT 24
Finished Mar 19 01:23:48 PM PDT 24
Peak memory 331232 kb
Host smart-bec36ad0-3fc1-4a0a-ab7e-174bfa2312a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1647064099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.1647064099 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.3288925663
Short name T202
Test name
Test status
Simulation time 117848839129 ps
CPU time 788.22 seconds
Started Mar 19 01:05:43 PM PDT 24
Finished Mar 19 01:18:52 PM PDT 24
Peak memory 293528 kb
Host smart-867ea18f-c2d5-4e94-b06e-7cb7c85675ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3288925663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.3288925663 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.13604469
Short name T1052
Test name
Test status
Simulation time 399145032613 ps
CPU time 4832.99 seconds
Started Mar 19 01:05:43 PM PDT 24
Finished Mar 19 02:26:17 PM PDT 24
Peak memory 648448 kb
Host smart-db8d88c4-f44c-445c-9f99-a67ab84bfd62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=13604469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.13604469 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.3033304447
Short name T692
Test name
Test status
Simulation time 436070228124 ps
CPU time 4449.77 seconds
Started Mar 19 01:05:44 PM PDT 24
Finished Mar 19 02:19:54 PM PDT 24
Peak memory 567428 kb
Host smart-853b76fb-bf20-41a7-84e4-ca58dbc4f283
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3033304447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.3033304447 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.1365687540
Short name T50
Test name
Test status
Simulation time 182328793 ps
CPU time 0.83 seconds
Started Mar 19 01:05:56 PM PDT 24
Finished Mar 19 01:05:57 PM PDT 24
Peak memory 205376 kb
Host smart-3c067a3a-dc08-430b-9289-08a9cf530ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365687540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1365687540 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.1722232089
Short name T691
Test name
Test status
Simulation time 8183792067 ps
CPU time 55.85 seconds
Started Mar 19 01:05:47 PM PDT 24
Finished Mar 19 01:06:43 PM PDT 24
Peak memory 223516 kb
Host smart-99eb832f-5c8b-4180-a9c7-b8e224fba3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722232089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.1722232089 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.1726416906
Short name T587
Test name
Test status
Simulation time 29543802926 ps
CPU time 626.52 seconds
Started Mar 19 01:05:44 PM PDT 24
Finished Mar 19 01:16:11 PM PDT 24
Peak memory 231804 kb
Host smart-944dd641-e535-40bc-a500-5f5528a37f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726416906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.1726416906 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.1649993194
Short name T729
Test name
Test status
Simulation time 6346891578 ps
CPU time 74.14 seconds
Started Mar 19 01:05:52 PM PDT 24
Finished Mar 19 01:07:07 PM PDT 24
Peak memory 226840 kb
Host smart-8fd322ef-1e6a-4d38-b07c-d20555dc78d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649993194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.1649993194 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.2136403576
Short name T541
Test name
Test status
Simulation time 26500871249 ps
CPU time 392.87 seconds
Started Mar 19 01:05:52 PM PDT 24
Finished Mar 19 01:12:25 PM PDT 24
Peak memory 256916 kb
Host smart-9eabd777-622b-4955-8b96-46e278d35f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136403576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2136403576 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.2065777882
Short name T908
Test name
Test status
Simulation time 1719607251 ps
CPU time 3.33 seconds
Started Mar 19 01:05:57 PM PDT 24
Finished Mar 19 01:06:01 PM PDT 24
Peak memory 207424 kb
Host smart-4f388147-e357-4253-92e6-14a8bd9bf3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065777882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2065777882 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.1117259225
Short name T512
Test name
Test status
Simulation time 44689211 ps
CPU time 1.33 seconds
Started Mar 19 01:05:52 PM PDT 24
Finished Mar 19 01:05:53 PM PDT 24
Peak memory 215860 kb
Host smart-c958fef3-69bf-46e9-a346-3e4f0aa554f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117259225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.1117259225 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.2556468672
Short name T925
Test name
Test status
Simulation time 132986423152 ps
CPU time 1511.81 seconds
Started Mar 19 01:05:44 PM PDT 24
Finished Mar 19 01:30:56 PM PDT 24
Peak memory 358772 kb
Host smart-9fe24136-f5f6-4014-889b-fe7f1812467d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556468672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a
nd_output.2556468672 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.2594886513
Short name T830
Test name
Test status
Simulation time 10931091354 ps
CPU time 280.71 seconds
Started Mar 19 01:05:48 PM PDT 24
Finished Mar 19 01:10:29 PM PDT 24
Peak memory 244476 kb
Host smart-53a80aba-67bc-4982-b350-20080fb9ae54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594886513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.2594886513 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.634708017
Short name T1035
Test name
Test status
Simulation time 2642822017 ps
CPU time 41.84 seconds
Started Mar 19 01:05:43 PM PDT 24
Finished Mar 19 01:06:25 PM PDT 24
Peak memory 219600 kb
Host smart-8f3927e2-1415-4f0e-a60e-b3f28d5be6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634708017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.634708017 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.779449421
Short name T46
Test name
Test status
Simulation time 45633085953 ps
CPU time 850.59 seconds
Started Mar 19 01:05:54 PM PDT 24
Finished Mar 19 01:20:05 PM PDT 24
Peak memory 306224 kb
Host smart-481ad028-5dd3-4f17-b86c-85d9377d5c6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=779449421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.779449421 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.3837384500
Short name T826
Test name
Test status
Simulation time 173524917 ps
CPU time 4.29 seconds
Started Mar 19 01:05:44 PM PDT 24
Finished Mar 19 01:05:49 PM PDT 24
Peak memory 215884 kb
Host smart-f15914aa-b1f2-4e53-9f6e-79e5a6f8ea0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837384500 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.kmac_test_vectors_kmac.3837384500 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.2493967884
Short name T913
Test name
Test status
Simulation time 975890249 ps
CPU time 4.4 seconds
Started Mar 19 01:05:44 PM PDT 24
Finished Mar 19 01:05:49 PM PDT 24
Peak memory 215836 kb
Host smart-c456c0a5-7237-48aa-8f87-b3bed4080f50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493967884 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.kmac_test_vectors_kmac_xof.2493967884 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.2645100102
Short name T410
Test name
Test status
Simulation time 20030360639 ps
CPU time 1642.02 seconds
Started Mar 19 01:05:47 PM PDT 24
Finished Mar 19 01:33:10 PM PDT 24
Peak memory 400036 kb
Host smart-79b7d65c-99b7-4a0f-80b2-a1d3500439e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2645100102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.2645100102 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.3674894569
Short name T658
Test name
Test status
Simulation time 45207724167 ps
CPU time 1482.25 seconds
Started Mar 19 01:05:44 PM PDT 24
Finished Mar 19 01:30:26 PM PDT 24
Peak memory 386980 kb
Host smart-ca145139-6ac0-4dee-9d30-5fb261cc2489
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3674894569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.3674894569 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.359137619
Short name T749
Test name
Test status
Simulation time 48073126092 ps
CPU time 1252.65 seconds
Started Mar 19 01:05:44 PM PDT 24
Finished Mar 19 01:26:37 PM PDT 24
Peak memory 330400 kb
Host smart-af6dc7e2-3f39-4308-80bc-41cb20fba7f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=359137619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.359137619 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.1916033404
Short name T1068
Test name
Test status
Simulation time 131844014059 ps
CPU time 898.16 seconds
Started Mar 19 01:05:43 PM PDT 24
Finished Mar 19 01:20:42 PM PDT 24
Peak memory 297100 kb
Host smart-37c4f47e-0ad2-400c-878c-c387a77712d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1916033404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.1916033404 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.3453055675
Short name T236
Test name
Test status
Simulation time 425704262830 ps
CPU time 4036.26 seconds
Started Mar 19 01:05:41 PM PDT 24
Finished Mar 19 02:12:58 PM PDT 24
Peak memory 654704 kb
Host smart-1438125e-b811-42cf-af90-31b628b17328
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3453055675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.3453055675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.2615051841
Short name T842
Test name
Test status
Simulation time 303535901998 ps
CPU time 4378.26 seconds
Started Mar 19 01:05:44 PM PDT 24
Finished Mar 19 02:18:43 PM PDT 24
Peak memory 557400 kb
Host smart-f34746af-31d4-4d8c-a371-544610370354
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2615051841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.2615051841 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.4082044048
Short name T896
Test name
Test status
Simulation time 27778667 ps
CPU time 0.75 seconds
Started Mar 19 01:05:56 PM PDT 24
Finished Mar 19 01:05:57 PM PDT 24
Peak memory 205332 kb
Host smart-bc22e925-e4a2-4fc1-be5b-332b2835b3d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082044048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.4082044048 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.3824698571
Short name T650
Test name
Test status
Simulation time 9611598772 ps
CPU time 210.99 seconds
Started Mar 19 01:05:55 PM PDT 24
Finished Mar 19 01:09:26 PM PDT 24
Peak memory 240376 kb
Host smart-eef60321-685f-4adb-9a6b-c37e37a559be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824698571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3824698571 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.1363416692
Short name T683
Test name
Test status
Simulation time 8239383657 ps
CPU time 564.59 seconds
Started Mar 19 01:05:56 PM PDT 24
Finished Mar 19 01:15:21 PM PDT 24
Peak memory 231376 kb
Host smart-4030f654-e01e-48af-8d29-9e11afe2e965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363416692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.1363416692 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.2089087069
Short name T151
Test name
Test status
Simulation time 23814995996 ps
CPU time 149.85 seconds
Started Mar 19 01:05:57 PM PDT 24
Finished Mar 19 01:08:27 PM PDT 24
Peak memory 233856 kb
Host smart-6d942045-0d6e-41e3-aa3b-a3c01c3db2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089087069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.2089087069 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.2678427827
Short name T300
Test name
Test status
Simulation time 14780113873 ps
CPU time 279.1 seconds
Started Mar 19 01:05:57 PM PDT 24
Finished Mar 19 01:10:36 PM PDT 24
Peak memory 252812 kb
Host smart-7ad41896-c22a-41bb-83d1-27c368315b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678427827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2678427827 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.3801484550
Short name T76
Test name
Test status
Simulation time 241603190 ps
CPU time 1.39 seconds
Started Mar 19 01:05:56 PM PDT 24
Finished Mar 19 01:05:58 PM PDT 24
Peak memory 207188 kb
Host smart-a081e46a-2461-4d10-adc2-914794a26e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801484550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.3801484550 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.82168581
Short name T421
Test name
Test status
Simulation time 2702112600 ps
CPU time 27.28 seconds
Started Mar 19 01:05:52 PM PDT 24
Finished Mar 19 01:06:20 PM PDT 24
Peak memory 232364 kb
Host smart-a55d9399-9bd9-4fee-a3d4-84714bf3daef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82168581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.82168581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.1614936523
Short name T560
Test name
Test status
Simulation time 388950262924 ps
CPU time 2760.25 seconds
Started Mar 19 01:05:54 PM PDT 24
Finished Mar 19 01:51:54 PM PDT 24
Peak memory 487456 kb
Host smart-b703157f-1a75-4b4a-84e4-57cc40cf5c19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614936523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.1614936523 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.62192429
Short name T374
Test name
Test status
Simulation time 27075067821 ps
CPU time 148.02 seconds
Started Mar 19 01:05:56 PM PDT 24
Finished Mar 19 01:08:24 PM PDT 24
Peak memory 230104 kb
Host smart-fb8acd6b-05b7-4bf0-873b-d1a0068f8436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62192429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.62192429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.506708657
Short name T898
Test name
Test status
Simulation time 783444929 ps
CPU time 17.78 seconds
Started Mar 19 01:05:58 PM PDT 24
Finished Mar 19 01:06:16 PM PDT 24
Peak memory 222036 kb
Host smart-86f9f9fa-f4f0-4663-bc52-1a94fb505042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506708657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.506708657 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.1331102793
Short name T496
Test name
Test status
Simulation time 146866289480 ps
CPU time 1473.15 seconds
Started Mar 19 01:05:55 PM PDT 24
Finished Mar 19 01:30:28 PM PDT 24
Peak memory 404280 kb
Host smart-07a014dd-0ca7-4038-8e06-e7202206edd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1331102793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.1331102793 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.1445937708
Short name T385
Test name
Test status
Simulation time 505418324 ps
CPU time 4.63 seconds
Started Mar 19 01:05:53 PM PDT 24
Finished Mar 19 01:05:58 PM PDT 24
Peak memory 215944 kb
Host smart-f807a94a-5b7c-466b-83e3-70ec3f31c5cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445937708 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.kmac_test_vectors_kmac.1445937708 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.4264574197
Short name T624
Test name
Test status
Simulation time 1105384278 ps
CPU time 5.26 seconds
Started Mar 19 01:05:56 PM PDT 24
Finished Mar 19 01:06:01 PM PDT 24
Peak memory 215804 kb
Host smart-424b362c-60df-434b-a466-cc61f9a56ba2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264574197 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.4264574197 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.1784069000
Short name T1007
Test name
Test status
Simulation time 129444746852 ps
CPU time 1715.55 seconds
Started Mar 19 01:05:53 PM PDT 24
Finished Mar 19 01:34:29 PM PDT 24
Peak memory 391684 kb
Host smart-a70f950a-23cd-45f7-8038-d8f6980531e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1784069000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.1784069000 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.2490503177
Short name T94
Test name
Test status
Simulation time 35481674176 ps
CPU time 1401.63 seconds
Started Mar 19 01:05:56 PM PDT 24
Finished Mar 19 01:29:18 PM PDT 24
Peak memory 366508 kb
Host smart-21119364-82de-450c-8c25-8350eee4e512
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2490503177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.2490503177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.1220015754
Short name T519
Test name
Test status
Simulation time 13808529602 ps
CPU time 1160.98 seconds
Started Mar 19 01:05:54 PM PDT 24
Finished Mar 19 01:25:15 PM PDT 24
Peak memory 338548 kb
Host smart-5917e69e-f6ba-4457-a333-9e6ddb514419
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1220015754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.1220015754 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.1914187976
Short name T186
Test name
Test status
Simulation time 9979857356 ps
CPU time 822.58 seconds
Started Mar 19 01:05:53 PM PDT 24
Finished Mar 19 01:19:35 PM PDT 24
Peak memory 296872 kb
Host smart-6872efd8-f522-49e7-8154-bf2a80d28768
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1914187976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.1914187976 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.3339216829
Short name T675
Test name
Test status
Simulation time 200253299809 ps
CPU time 4305.81 seconds
Started Mar 19 01:05:54 PM PDT 24
Finished Mar 19 02:17:41 PM PDT 24
Peak memory 634048 kb
Host smart-c4d4dd6a-ff49-4254-87c5-a50e1b44c1a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3339216829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.3339216829 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.1775819209
Short name T875
Test name
Test status
Simulation time 143247133572 ps
CPU time 3320.89 seconds
Started Mar 19 01:05:57 PM PDT 24
Finished Mar 19 02:01:19 PM PDT 24
Peak memory 555464 kb
Host smart-0091cf2a-dba3-4a7f-a278-fcc87f7a4569
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1775819209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.1775819209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.2585149944
Short name T772
Test name
Test status
Simulation time 97470843 ps
CPU time 0.89 seconds
Started Mar 19 01:06:02 PM PDT 24
Finished Mar 19 01:06:03 PM PDT 24
Peak memory 205308 kb
Host smart-239f13e5-e312-4e64-8dfd-b189a6a3abe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585149944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2585149944 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.706603706
Short name T966
Test name
Test status
Simulation time 5815077487 ps
CPU time 102.16 seconds
Started Mar 19 01:06:10 PM PDT 24
Finished Mar 19 01:07:52 PM PDT 24
Peak memory 231396 kb
Host smart-862f3a0d-514e-444f-9634-dd46c0f22ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706603706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.706603706 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.211822511
Short name T466
Test name
Test status
Simulation time 6872830173 ps
CPU time 88.31 seconds
Started Mar 19 01:06:05 PM PDT 24
Finished Mar 19 01:07:33 PM PDT 24
Peak memory 232208 kb
Host smart-d4a3f95b-43b2-4932-bd18-9d851766639c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211822511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.211822511 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.3713683285
Short name T902
Test name
Test status
Simulation time 7054325313 ps
CPU time 41.47 seconds
Started Mar 19 01:06:02 PM PDT 24
Finished Mar 19 01:06:44 PM PDT 24
Peak memory 222464 kb
Host smart-03a6ecc1-e409-4fa9-af07-cd5b2e11c66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713683285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.3713683285 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.412927251
Short name T368
Test name
Test status
Simulation time 4407517813 ps
CPU time 171.93 seconds
Started Mar 19 01:06:01 PM PDT 24
Finished Mar 19 01:08:53 PM PDT 24
Peak memory 248756 kb
Host smart-18402cd6-a59b-4aa5-821a-18a51e8f3f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412927251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.412927251 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.2462228979
Short name T777
Test name
Test status
Simulation time 2129896958 ps
CPU time 5.66 seconds
Started Mar 19 01:06:03 PM PDT 24
Finished Mar 19 01:06:09 PM PDT 24
Peak memory 215784 kb
Host smart-ca2fa525-f47b-433d-8ba7-85b1af560dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462228979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2462228979 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.3104342813
Short name T55
Test name
Test status
Simulation time 2165443329 ps
CPU time 12.5 seconds
Started Mar 19 01:06:03 PM PDT 24
Finished Mar 19 01:06:16 PM PDT 24
Peak memory 224216 kb
Host smart-913d2060-4ef0-4dd3-a9c6-622bb7d1cde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104342813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.3104342813 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.3814290566
Short name T505
Test name
Test status
Simulation time 12813786482 ps
CPU time 1153.85 seconds
Started Mar 19 01:06:03 PM PDT 24
Finished Mar 19 01:25:17 PM PDT 24
Peak memory 339416 kb
Host smart-d4524c41-89b5-4c61-a564-63c8679d677c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814290566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.3814290566 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.2446296457
Short name T973
Test name
Test status
Simulation time 59115472472 ps
CPU time 297.98 seconds
Started Mar 19 01:06:02 PM PDT 24
Finished Mar 19 01:11:00 PM PDT 24
Peak memory 241532 kb
Host smart-17bacd6e-a281-4aec-9956-86a6a385b7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446296457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.2446296457 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.1144483890
Short name T200
Test name
Test status
Simulation time 5711261208 ps
CPU time 41.45 seconds
Started Mar 19 01:05:55 PM PDT 24
Finished Mar 19 01:06:37 PM PDT 24
Peak memory 219464 kb
Host smart-bcd50202-8722-4a32-a31e-e4b3ed690ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144483890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1144483890 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.3156445688
Short name T464
Test name
Test status
Simulation time 16022884303 ps
CPU time 336.3 seconds
Started Mar 19 01:06:02 PM PDT 24
Finished Mar 19 01:11:38 PM PDT 24
Peak memory 255816 kb
Host smart-162834db-ed59-48ed-8fc5-428d6c97d44c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3156445688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3156445688 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.209380634
Short name T225
Test name
Test status
Simulation time 745327302 ps
CPU time 4.81 seconds
Started Mar 19 01:06:02 PM PDT 24
Finished Mar 19 01:06:07 PM PDT 24
Peak memory 215940 kb
Host smart-630d378f-aa0e-4d67-a7f3-e1d1bca68b0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209380634 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.kmac_test_vectors_kmac.209380634 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.3652993870
Short name T1038
Test name
Test status
Simulation time 1205495855 ps
CPU time 5.15 seconds
Started Mar 19 01:06:05 PM PDT 24
Finished Mar 19 01:06:10 PM PDT 24
Peak memory 215920 kb
Host smart-b12e3c8d-05d9-48a1-9346-c620238085cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652993870 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.kmac_test_vectors_kmac_xof.3652993870 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.461803794
Short name T746
Test name
Test status
Simulation time 1089440198767 ps
CPU time 2064.48 seconds
Started Mar 19 01:06:04 PM PDT 24
Finished Mar 19 01:40:29 PM PDT 24
Peak memory 396304 kb
Host smart-d342d7da-f656-4df0-a6df-16d5b56347a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=461803794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.461803794 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.4156395452
Short name T856
Test name
Test status
Simulation time 60661667566 ps
CPU time 1652.42 seconds
Started Mar 19 01:06:03 PM PDT 24
Finished Mar 19 01:33:36 PM PDT 24
Peak memory 371460 kb
Host smart-130b3632-f32e-4cf3-a482-6e4325eaf2bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4156395452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.4156395452 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.1340243973
Short name T329
Test name
Test status
Simulation time 63265364801 ps
CPU time 1277 seconds
Started Mar 19 01:06:04 PM PDT 24
Finished Mar 19 01:27:21 PM PDT 24
Peak memory 325968 kb
Host smart-fa6f67db-9715-4309-b1cf-30ef94bed424
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1340243973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.1340243973 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.2692787713
Short name T594
Test name
Test status
Simulation time 42888635289 ps
CPU time 889.98 seconds
Started Mar 19 01:06:04 PM PDT 24
Finished Mar 19 01:20:54 PM PDT 24
Peak memory 289840 kb
Host smart-5a547fa4-5de9-41b4-82c8-d217174d6cee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2692787713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.2692787713 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.3683877426
Short name T1069
Test name
Test status
Simulation time 717763673432 ps
CPU time 4909.07 seconds
Started Mar 19 01:06:02 PM PDT 24
Finished Mar 19 02:27:52 PM PDT 24
Peak memory 653384 kb
Host smart-e485ae70-2d96-4b00-8e9f-bba30c478365
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3683877426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.3683877426 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.3509093689
Short name T734
Test name
Test status
Simulation time 179282456280 ps
CPU time 3437.81 seconds
Started Mar 19 01:06:02 PM PDT 24
Finished Mar 19 02:03:21 PM PDT 24
Peak memory 555524 kb
Host smart-040ebfea-c637-40d4-b845-bb3e8a1e6301
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3509093689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.3509093689 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.41641597
Short name T720
Test name
Test status
Simulation time 22332213 ps
CPU time 0.83 seconds
Started Mar 19 01:06:14 PM PDT 24
Finished Mar 19 01:06:15 PM PDT 24
Peak memory 205396 kb
Host smart-066a8eeb-85e3-4fb4-b932-db891b21b4fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41641597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.41641597 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.925684925
Short name T299
Test name
Test status
Simulation time 976697705 ps
CPU time 18.05 seconds
Started Mar 19 01:06:14 PM PDT 24
Finished Mar 19 01:06:32 PM PDT 24
Peak memory 218024 kb
Host smart-4db9bd52-4062-49c3-9632-b34dccde9c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925684925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.925684925 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.3842094987
Short name T965
Test name
Test status
Simulation time 7169611003 ps
CPU time 215.49 seconds
Started Mar 19 01:06:16 PM PDT 24
Finished Mar 19 01:09:52 PM PDT 24
Peak memory 243476 kb
Host smart-0f7d86de-69cc-4c52-95a3-7d4b8d9d0306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842094987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3842094987 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.3461057093
Short name T944
Test name
Test status
Simulation time 6521616688 ps
CPU time 44.82 seconds
Started Mar 19 01:06:16 PM PDT 24
Finished Mar 19 01:07:01 PM PDT 24
Peak memory 232736 kb
Host smart-db28f3c0-1533-4e32-90f3-0b7e88f67018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461057093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.3461057093 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.2632424900
Short name T873
Test name
Test status
Simulation time 9971820927 ps
CPU time 5.66 seconds
Started Mar 19 01:06:14 PM PDT 24
Finished Mar 19 01:06:20 PM PDT 24
Peak memory 207780 kb
Host smart-6af1896b-dbca-4f16-9aed-2ea5d050e3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632424900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2632424900 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.2198812248
Short name T846
Test name
Test status
Simulation time 41275640 ps
CPU time 1.38 seconds
Started Mar 19 01:06:21 PM PDT 24
Finished Mar 19 01:06:22 PM PDT 24
Peak memory 217532 kb
Host smart-91b9a24c-6651-4be1-b103-1e2b540d40dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198812248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2198812248 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.553969014
Short name T565
Test name
Test status
Simulation time 12320309079 ps
CPU time 492.92 seconds
Started Mar 19 01:06:05 PM PDT 24
Finished Mar 19 01:14:18 PM PDT 24
Peak memory 273560 kb
Host smart-f954369e-c231-4916-bd95-813d56037de7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553969014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_an
d_output.553969014 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.3768999689
Short name T13
Test name
Test status
Simulation time 2484758088 ps
CPU time 188.73 seconds
Started Mar 19 01:06:03 PM PDT 24
Finished Mar 19 01:09:12 PM PDT 24
Peak memory 240524 kb
Host smart-ba67be2f-ea49-42cf-9d97-1f1f3a9267e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768999689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.3768999689 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.85312309
Short name T92
Test name
Test status
Simulation time 14707829935 ps
CPU time 62.97 seconds
Started Mar 19 01:06:04 PM PDT 24
Finished Mar 19 01:07:07 PM PDT 24
Peak memory 219668 kb
Host smart-f55bb7c2-43b9-4e55-8331-e5b17f632763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85312309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.85312309 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.2919406039
Short name T618
Test name
Test status
Simulation time 180526864 ps
CPU time 4.64 seconds
Started Mar 19 01:06:15 PM PDT 24
Finished Mar 19 01:06:19 PM PDT 24
Peak memory 215944 kb
Host smart-cb0051fe-7f1a-4b5d-a1bc-780f1b3e73db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919406039 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.2919406039 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.1125893237
Short name T707
Test name
Test status
Simulation time 617574767 ps
CPU time 4.19 seconds
Started Mar 19 01:06:16 PM PDT 24
Finished Mar 19 01:06:20 PM PDT 24
Peak memory 215912 kb
Host smart-0849f2ff-3c33-4bc4-a827-63b98ab400e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125893237 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.kmac_test_vectors_kmac_xof.1125893237 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.1842026580
Short name T158
Test name
Test status
Simulation time 1041653790986 ps
CPU time 1912.05 seconds
Started Mar 19 01:06:05 PM PDT 24
Finished Mar 19 01:37:58 PM PDT 24
Peak memory 388524 kb
Host smart-73519236-f861-42cd-b3e7-c28d7abfa7f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1842026580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.1842026580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.3686055353
Short name T990
Test name
Test status
Simulation time 62430823419 ps
CPU time 1663.32 seconds
Started Mar 19 01:06:16 PM PDT 24
Finished Mar 19 01:33:59 PM PDT 24
Peak memory 366612 kb
Host smart-84ee44a0-7ff5-4e5a-bcff-7e8f99c04801
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3686055353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.3686055353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.1481351116
Short name T744
Test name
Test status
Simulation time 62143424251 ps
CPU time 1196.33 seconds
Started Mar 19 01:06:14 PM PDT 24
Finished Mar 19 01:26:11 PM PDT 24
Peak memory 328960 kb
Host smart-42770c10-8666-47e5-bcb6-a0e593348aa2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1481351116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.1481351116 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.204386699
Short name T943
Test name
Test status
Simulation time 43239992219 ps
CPU time 946.71 seconds
Started Mar 19 01:06:15 PM PDT 24
Finished Mar 19 01:22:02 PM PDT 24
Peak memory 295100 kb
Host smart-d0cc89f2-16e2-4aea-88d2-1d440b3b2eda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=204386699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.204386699 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.2485978782
Short name T1028
Test name
Test status
Simulation time 51016127228 ps
CPU time 4188.16 seconds
Started Mar 19 01:06:15 PM PDT 24
Finished Mar 19 02:16:04 PM PDT 24
Peak memory 653404 kb
Host smart-fbe328cf-7607-4ab7-91d5-a398190defcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2485978782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.2485978782 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.574019102
Short name T717
Test name
Test status
Simulation time 45020294107 ps
CPU time 3363.08 seconds
Started Mar 19 01:06:15 PM PDT 24
Finished Mar 19 02:02:19 PM PDT 24
Peak memory 569188 kb
Host smart-4e3fd345-3576-4944-8892-75628db5fb18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=574019102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.574019102 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.2252770202
Short name T513
Test name
Test status
Simulation time 60352553 ps
CPU time 0.82 seconds
Started Mar 19 01:06:30 PM PDT 24
Finished Mar 19 01:06:32 PM PDT 24
Peak memory 205392 kb
Host smart-2947dc5d-4860-4ce2-acd3-0bd45b7b7e97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252770202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.2252770202 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.3848429468
Short name T483
Test name
Test status
Simulation time 5384203407 ps
CPU time 149.44 seconds
Started Mar 19 01:06:30 PM PDT 24
Finished Mar 19 01:09:00 PM PDT 24
Peak memory 235568 kb
Host smart-9ac04dc8-3bc4-4f57-8898-3f0315c51d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848429468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.3848429468 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.585312998
Short name T269
Test name
Test status
Simulation time 9248555737 ps
CPU time 409.7 seconds
Started Mar 19 01:06:31 PM PDT 24
Finished Mar 19 01:13:21 PM PDT 24
Peak memory 232688 kb
Host smart-962372c7-ae76-41e8-898d-6a39166bbdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585312998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.585312998 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.2670585172
Short name T754
Test name
Test status
Simulation time 8562472188 ps
CPU time 257.32 seconds
Started Mar 19 01:06:30 PM PDT 24
Finished Mar 19 01:10:48 PM PDT 24
Peak memory 242120 kb
Host smart-c5891880-65cd-468f-badd-8535a94b43ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670585172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.2670585172 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.2940860890
Short name T756
Test name
Test status
Simulation time 3787745558 ps
CPU time 89.84 seconds
Started Mar 19 01:06:29 PM PDT 24
Finished Mar 19 01:07:59 PM PDT 24
Peak memory 240564 kb
Host smart-627c3935-dfb1-4b1f-823d-ff415882b128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940860890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.2940860890 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.890487447
Short name T597
Test name
Test status
Simulation time 591801384 ps
CPU time 2.21 seconds
Started Mar 19 01:06:30 PM PDT 24
Finished Mar 19 01:06:33 PM PDT 24
Peak memory 207484 kb
Host smart-c7348e15-cf4d-4c3c-b326-354b81d41403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890487447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.890487447 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.1979642445
Short name T56
Test name
Test status
Simulation time 733308529 ps
CPU time 8.53 seconds
Started Mar 19 01:06:30 PM PDT 24
Finished Mar 19 01:06:39 PM PDT 24
Peak memory 224152 kb
Host smart-ea03ea7d-22a9-4900-be2d-32d448df3532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979642445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1979642445 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.2227769281
Short name T887
Test name
Test status
Simulation time 108299009966 ps
CPU time 1670.63 seconds
Started Mar 19 01:06:15 PM PDT 24
Finished Mar 19 01:34:06 PM PDT 24
Peak memory 375248 kb
Host smart-f02edc8c-1f56-45f1-9480-8e421cca0e83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227769281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.2227769281 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.2874660924
Short name T546
Test name
Test status
Simulation time 3327654649 ps
CPU time 70.87 seconds
Started Mar 19 01:06:30 PM PDT 24
Finished Mar 19 01:07:41 PM PDT 24
Peak memory 224804 kb
Host smart-beefb6fe-a40d-462e-9f28-1fbae8fcc308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874660924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.2874660924 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.1527984642
Short name T333
Test name
Test status
Simulation time 60011902 ps
CPU time 1.61 seconds
Started Mar 19 01:06:15 PM PDT 24
Finished Mar 19 01:06:17 PM PDT 24
Peak memory 221936 kb
Host smart-db8cc83e-ead0-47f5-8fc2-bcf277ac9fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527984642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1527984642 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.4012638202
Short name T206
Test name
Test status
Simulation time 181564835 ps
CPU time 4.87 seconds
Started Mar 19 01:06:28 PM PDT 24
Finished Mar 19 01:06:33 PM PDT 24
Peak memory 215892 kb
Host smart-98348a67-2f77-48ed-9d78-55b4c369cc03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012638202 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.4012638202 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.706397508
Short name T949
Test name
Test status
Simulation time 136961132 ps
CPU time 4.44 seconds
Started Mar 19 01:06:30 PM PDT 24
Finished Mar 19 01:06:34 PM PDT 24
Peak memory 215932 kb
Host smart-14c25a2a-6fb0-48cc-8f05-515279a0bd29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706397508 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.kmac_test_vectors_kmac_xof.706397508 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.4159428643
Short name T918
Test name
Test status
Simulation time 185771670234 ps
CPU time 1744.21 seconds
Started Mar 19 01:06:31 PM PDT 24
Finished Mar 19 01:35:35 PM PDT 24
Peak memory 392272 kb
Host smart-ad821e2d-e7f1-4b2f-b4c1-95a04aad699b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4159428643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.4159428643 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.2156576759
Short name T499
Test name
Test status
Simulation time 74429338735 ps
CPU time 1462.36 seconds
Started Mar 19 01:06:30 PM PDT 24
Finished Mar 19 01:30:53 PM PDT 24
Peak memory 377040 kb
Host smart-80f67d7e-cb5a-434c-870c-9493114bc086
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2156576759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.2156576759 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.2105092699
Short name T799
Test name
Test status
Simulation time 69800130454 ps
CPU time 1422.71 seconds
Started Mar 19 01:06:31 PM PDT 24
Finished Mar 19 01:30:14 PM PDT 24
Peak memory 333392 kb
Host smart-edcec49d-e873-41b5-8747-81270e9a5c5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2105092699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.2105092699 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.3703218914
Short name T93
Test name
Test status
Simulation time 131639515190 ps
CPU time 852.22 seconds
Started Mar 19 01:06:29 PM PDT 24
Finished Mar 19 01:20:42 PM PDT 24
Peak memory 288828 kb
Host smart-c8369254-244f-4b96-829b-1e03902c74c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3703218914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.3703218914 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.2519540149
Short name T718
Test name
Test status
Simulation time 777245246357 ps
CPU time 4876.38 seconds
Started Mar 19 01:06:29 PM PDT 24
Finished Mar 19 02:27:46 PM PDT 24
Peak memory 650372 kb
Host smart-fd888f3f-90c8-4757-b412-a4c1b2e11c8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2519540149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.2519540149 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.3694898368
Short name T947
Test name
Test status
Simulation time 148160326185 ps
CPU time 4019.84 seconds
Started Mar 19 01:06:31 PM PDT 24
Finished Mar 19 02:13:31 PM PDT 24
Peak memory 577336 kb
Host smart-459d6e62-f942-4e6d-89fe-d6e6f7d9de3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3694898368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.3694898368 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.1207489442
Short name T323
Test name
Test status
Simulation time 16708375 ps
CPU time 0.8 seconds
Started Mar 19 01:06:43 PM PDT 24
Finished Mar 19 01:06:45 PM PDT 24
Peak memory 205416 kb
Host smart-886f5bec-88a4-4198-9dff-df24f727aa94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207489442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1207489442 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.1502400710
Short name T694
Test name
Test status
Simulation time 21015496523 ps
CPU time 228.95 seconds
Started Mar 19 01:06:29 PM PDT 24
Finished Mar 19 01:10:19 PM PDT 24
Peak memory 239668 kb
Host smart-7b50eaa0-a6a9-4f50-9c20-7abc0501ef49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502400710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.1502400710 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.4169351414
Short name T477
Test name
Test status
Simulation time 11207456687 ps
CPU time 125.23 seconds
Started Mar 19 01:06:30 PM PDT 24
Finished Mar 19 01:08:36 PM PDT 24
Peak memory 222472 kb
Host smart-b111b3f2-3941-43ed-9164-312f190356f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169351414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.4169351414 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.3730653853
Short name T684
Test name
Test status
Simulation time 11268039132 ps
CPU time 202.71 seconds
Started Mar 19 01:06:44 PM PDT 24
Finished Mar 19 01:10:08 PM PDT 24
Peak memory 241856 kb
Host smart-d87cde36-9df0-44a6-8761-6711907589c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730653853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.3730653853 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_key_error.3775087717
Short name T379
Test name
Test status
Simulation time 793314378 ps
CPU time 4.2 seconds
Started Mar 19 01:06:40 PM PDT 24
Finished Mar 19 01:06:44 PM PDT 24
Peak memory 207476 kb
Host smart-8ff3c637-d45e-481a-b686-ac8ede835e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775087717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3775087717 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.3925502565
Short name T539
Test name
Test status
Simulation time 129649882 ps
CPU time 1.28 seconds
Started Mar 19 01:06:44 PM PDT 24
Finished Mar 19 01:06:45 PM PDT 24
Peak memory 220220 kb
Host smart-5e50b9f2-fb4c-4bfa-bd97-86576a89fa1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925502565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.3925502565 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.2617710021
Short name T1
Test name
Test status
Simulation time 104613435221 ps
CPU time 1441.43 seconds
Started Mar 19 01:06:30 PM PDT 24
Finished Mar 19 01:30:32 PM PDT 24
Peak memory 360696 kb
Host smart-bf63bdec-5859-4d2e-a5cc-2e782e9c558a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617710021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.2617710021 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.760999032
Short name T573
Test name
Test status
Simulation time 315510147 ps
CPU time 23.54 seconds
Started Mar 19 01:06:30 PM PDT 24
Finished Mar 19 01:06:54 PM PDT 24
Peak memory 221624 kb
Host smart-a7f9a936-9a04-4b9f-81d1-a9ee55658835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760999032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.760999032 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.2737859945
Short name T474
Test name
Test status
Simulation time 413317240 ps
CPU time 20.57 seconds
Started Mar 19 01:06:29 PM PDT 24
Finished Mar 19 01:06:49 PM PDT 24
Peak memory 218144 kb
Host smart-045eaa51-54be-41b4-82c0-7e43af58a6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737859945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.2737859945 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.551233063
Short name T460
Test name
Test status
Simulation time 4056557362 ps
CPU time 322.86 seconds
Started Mar 19 01:06:41 PM PDT 24
Finished Mar 19 01:12:04 PM PDT 24
Peak memory 252604 kb
Host smart-1a0add54-5f3c-483e-86eb-0a89eeb08e79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=551233063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.551233063 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_stress_all_with_rand_reset.2237698259
Short name T123
Test name
Test status
Simulation time 221094143309 ps
CPU time 1334.52 seconds
Started Mar 19 01:06:40 PM PDT 24
Finished Mar 19 01:28:55 PM PDT 24
Peak memory 322728 kb
Host smart-14f44779-3525-4ac1-82b6-8d1432b09733
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2237698259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all_with_rand_reset.2237698259 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.678613370
Short name T670
Test name
Test status
Simulation time 2263979202 ps
CPU time 5.98 seconds
Started Mar 19 01:06:29 PM PDT 24
Finished Mar 19 01:06:35 PM PDT 24
Peak memory 215920 kb
Host smart-a9c871ac-4475-4f5e-b07d-fbdeaa56172c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678613370 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.kmac_test_vectors_kmac.678613370 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.4193750379
Short name T580
Test name
Test status
Simulation time 764997244 ps
CPU time 4.79 seconds
Started Mar 19 01:06:30 PM PDT 24
Finished Mar 19 01:06:35 PM PDT 24
Peak memory 209292 kb
Host smart-de26ed58-8df9-4e2c-9b08-66d98fcece4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193750379 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.4193750379 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.402590466
Short name T878
Test name
Test status
Simulation time 95638859883 ps
CPU time 1964.84 seconds
Started Mar 19 01:06:31 PM PDT 24
Finished Mar 19 01:39:16 PM PDT 24
Peak memory 396364 kb
Host smart-069d9d96-c834-46fe-9438-ecd4bf874a81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=402590466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.402590466 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.158452789
Short name T469
Test name
Test status
Simulation time 95462073047 ps
CPU time 1829.92 seconds
Started Mar 19 01:06:31 PM PDT 24
Finished Mar 19 01:37:01 PM PDT 24
Peak memory 374456 kb
Host smart-c4becd0e-9471-4d50-b82d-c21f84f55a7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=158452789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.158452789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.2346562588
Short name T537
Test name
Test status
Simulation time 49930873474 ps
CPU time 1144.48 seconds
Started Mar 19 01:06:32 PM PDT 24
Finished Mar 19 01:25:37 PM PDT 24
Peak memory 331612 kb
Host smart-9c3a2313-cd4d-4d96-ab96-22490b12740d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2346562588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.2346562588 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.2920191630
Short name T742
Test name
Test status
Simulation time 134306469761 ps
CPU time 903.58 seconds
Started Mar 19 01:06:31 PM PDT 24
Finished Mar 19 01:21:35 PM PDT 24
Peak memory 292496 kb
Host smart-33466513-9515-4961-ab06-1273c1bdc208
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2920191630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.2920191630 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.733668692
Short name T858
Test name
Test status
Simulation time 1220296501059 ps
CPU time 5918.04 seconds
Started Mar 19 01:06:31 PM PDT 24
Finished Mar 19 02:45:10 PM PDT 24
Peak memory 648944 kb
Host smart-59f04525-442c-4e67-a803-b9d43912902f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=733668692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.733668692 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.2516712875
Short name T785
Test name
Test status
Simulation time 193269552856 ps
CPU time 3842.46 seconds
Started Mar 19 01:06:29 PM PDT 24
Finished Mar 19 02:10:32 PM PDT 24
Peak memory 549760 kb
Host smart-04399ff9-f358-42f2-9207-2e46af1e1b5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2516712875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.2516712875 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.706584027
Short name T1032
Test name
Test status
Simulation time 17678738 ps
CPU time 0.78 seconds
Started Mar 19 01:06:51 PM PDT 24
Finished Mar 19 01:06:52 PM PDT 24
Peak memory 205360 kb
Host smart-0a12db22-1bb7-4176-9f92-e4ce117a2a5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706584027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.706584027 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.877031527
Short name T382
Test name
Test status
Simulation time 8512741135 ps
CPU time 136.32 seconds
Started Mar 19 01:06:40 PM PDT 24
Finished Mar 19 01:08:57 PM PDT 24
Peak memory 233024 kb
Host smart-f2ca9161-eb7b-46ec-bd27-85c16fa9054f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877031527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.877031527 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.4262350645
Short name T851
Test name
Test status
Simulation time 33225436945 ps
CPU time 730.51 seconds
Started Mar 19 01:06:42 PM PDT 24
Finished Mar 19 01:18:53 PM PDT 24
Peak memory 232032 kb
Host smart-a45d9025-47d9-4a36-bf50-ab19f2a3a18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262350645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.4262350645 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.2489131972
Short name T639
Test name
Test status
Simulation time 58440986442 ps
CPU time 171.94 seconds
Started Mar 19 01:06:39 PM PDT 24
Finished Mar 19 01:09:31 PM PDT 24
Peak memory 236472 kb
Host smart-3f96c5e2-dc85-412b-9b2f-cc1990f0ef4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489131972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.2489131972 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.3471035129
Short name T622
Test name
Test status
Simulation time 1355582926 ps
CPU time 35.12 seconds
Started Mar 19 01:06:42 PM PDT 24
Finished Mar 19 01:07:17 PM PDT 24
Peak memory 238316 kb
Host smart-348b9e07-8e39-4414-bc71-1e6406cefe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471035129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3471035129 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.3805846255
Short name T938
Test name
Test status
Simulation time 1002567488 ps
CPU time 4.7 seconds
Started Mar 19 01:06:46 PM PDT 24
Finished Mar 19 01:06:52 PM PDT 24
Peak memory 207548 kb
Host smart-2606882d-dcb6-4057-924e-f01ed586f1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805846255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.3805846255 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.2472823972
Short name T525
Test name
Test status
Simulation time 179628702 ps
CPU time 1.4 seconds
Started Mar 19 01:06:44 PM PDT 24
Finished Mar 19 01:06:45 PM PDT 24
Peak memory 215828 kb
Host smart-31596f66-3984-40ee-b1e2-5741bdb4da5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472823972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2472823972 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.1338576880
Short name T189
Test name
Test status
Simulation time 110282954557 ps
CPU time 2180.45 seconds
Started Mar 19 01:06:44 PM PDT 24
Finished Mar 19 01:43:05 PM PDT 24
Peak memory 436820 kb
Host smart-c98e2c02-a22b-40bf-a9b6-2f0c049c006f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338576880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.1338576880 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.1562278292
Short name T751
Test name
Test status
Simulation time 2347697180 ps
CPU time 198.85 seconds
Started Mar 19 01:06:46 PM PDT 24
Finished Mar 19 01:10:07 PM PDT 24
Peak memory 237144 kb
Host smart-0ad0acb0-6010-415e-a0e6-05f628edf2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562278292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.1562278292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.1539487764
Short name T714
Test name
Test status
Simulation time 2089492632 ps
CPU time 41.78 seconds
Started Mar 19 01:06:50 PM PDT 24
Finished Mar 19 01:07:33 PM PDT 24
Peak memory 217268 kb
Host smart-d41d8f2a-c66f-48a0-b57c-6456fcb9fbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539487764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.1539487764 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.3213265771
Short name T529
Test name
Test status
Simulation time 51302708526 ps
CPU time 1456.98 seconds
Started Mar 19 01:06:39 PM PDT 24
Finished Mar 19 01:30:56 PM PDT 24
Peak memory 363324 kb
Host smart-22f5ce46-26c2-4dd9-9508-5b741c8ebb60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3213265771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.3213265771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.1079472190
Short name T981
Test name
Test status
Simulation time 236380703 ps
CPU time 5.08 seconds
Started Mar 19 01:06:38 PM PDT 24
Finished Mar 19 01:06:43 PM PDT 24
Peak memory 215916 kb
Host smart-40117a99-37d0-40e5-ae8f-db99446f8a09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079472190 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.kmac_test_vectors_kmac.1079472190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.346076247
Short name T413
Test name
Test status
Simulation time 174978540 ps
CPU time 4.63 seconds
Started Mar 19 01:06:41 PM PDT 24
Finished Mar 19 01:06:46 PM PDT 24
Peak memory 215944 kb
Host smart-802f3e51-f3fd-4d15-b909-70be6f56a284
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346076247 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.kmac_test_vectors_kmac_xof.346076247 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.2857381000
Short name T1060
Test name
Test status
Simulation time 65972941151 ps
CPU time 1765.72 seconds
Started Mar 19 01:06:42 PM PDT 24
Finished Mar 19 01:36:08 PM PDT 24
Peak memory 393980 kb
Host smart-18104f31-af63-479d-ad75-5fd06f710d74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2857381000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.2857381000 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.3344794021
Short name T192
Test name
Test status
Simulation time 17619530634 ps
CPU time 1504.96 seconds
Started Mar 19 01:06:37 PM PDT 24
Finished Mar 19 01:31:42 PM PDT 24
Peak memory 372044 kb
Host smart-571f5146-0ca9-4a3e-99ba-d4ee5c8dc22f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3344794021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.3344794021 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.2193736007
Short name T640
Test name
Test status
Simulation time 70617869918 ps
CPU time 1385.22 seconds
Started Mar 19 01:06:46 PM PDT 24
Finished Mar 19 01:29:52 PM PDT 24
Peak memory 336640 kb
Host smart-31c8704a-18cb-482a-8279-fa2b9bae9f7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2193736007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.2193736007 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.507608885
Short name T969
Test name
Test status
Simulation time 105833923045 ps
CPU time 761.88 seconds
Started Mar 19 01:06:40 PM PDT 24
Finished Mar 19 01:19:22 PM PDT 24
Peak memory 295744 kb
Host smart-126e24a1-a3ea-455b-9f69-ecaafbcba3b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=507608885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.507608885 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.2468732
Short name T958
Test name
Test status
Simulation time 50948223187 ps
CPU time 4223.76 seconds
Started Mar 19 01:06:42 PM PDT 24
Finished Mar 19 02:17:07 PM PDT 24
Peak memory 652420 kb
Host smart-08d97df8-e676-43ef-a798-e05e8b5a9e88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2468732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.2468732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_alert_test.2340933773
Short name T1010
Test name
Test status
Simulation time 24067671 ps
CPU time 0.8 seconds
Started Mar 19 01:06:48 PM PDT 24
Finished Mar 19 01:06:49 PM PDT 24
Peak memory 205420 kb
Host smart-2edb6de7-4cd3-40c5-9b7f-b1a41af3efb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340933773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.2340933773 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.2228014127
Short name T591
Test name
Test status
Simulation time 3045760984 ps
CPU time 168.77 seconds
Started Mar 19 01:06:48 PM PDT 24
Finished Mar 19 01:09:38 PM PDT 24
Peak memory 237864 kb
Host smart-a6544350-a644-407b-98fd-0b5f38ee5a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228014127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.2228014127 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.1697705689
Short name T129
Test name
Test status
Simulation time 2665633429 ps
CPU time 62.51 seconds
Started Mar 19 01:06:50 PM PDT 24
Finished Mar 19 01:07:54 PM PDT 24
Peak memory 219284 kb
Host smart-ecbdee9b-ef14-419d-bdc1-df9810396a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697705689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.1697705689 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.1479628339
Short name T314
Test name
Test status
Simulation time 3430640774 ps
CPU time 81.44 seconds
Started Mar 19 01:06:49 PM PDT 24
Finished Mar 19 01:08:10 PM PDT 24
Peak memory 228708 kb
Host smart-1c42cbad-539d-485d-8c23-be42e9414863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479628339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.1479628339 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.3222914095
Short name T786
Test name
Test status
Simulation time 5208916679 ps
CPU time 322.32 seconds
Started Mar 19 01:06:49 PM PDT 24
Finished Mar 19 01:12:11 PM PDT 24
Peak memory 256932 kb
Host smart-b62fb585-b16b-45c2-be64-2462a827627e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222914095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.3222914095 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.2023127659
Short name T890
Test name
Test status
Simulation time 1605143262 ps
CPU time 2.96 seconds
Started Mar 19 01:06:48 PM PDT 24
Finished Mar 19 01:06:51 PM PDT 24
Peak memory 207600 kb
Host smart-a31ff647-9a6f-4674-9b3f-b4284b784061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023127659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.2023127659 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.4074630343
Short name T1073
Test name
Test status
Simulation time 146381410 ps
CPU time 1.38 seconds
Started Mar 19 01:06:49 PM PDT 24
Finished Mar 19 01:06:53 PM PDT 24
Peak memory 215792 kb
Host smart-57e3eb16-9d89-45b0-9540-86784595614c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074630343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.4074630343 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.1966945337
Short name T727
Test name
Test status
Simulation time 27542212485 ps
CPU time 134.53 seconds
Started Mar 19 01:06:46 PM PDT 24
Finished Mar 19 01:09:02 PM PDT 24
Peak memory 227424 kb
Host smart-2a5936d4-f3d8-430e-b84c-c36133b8404c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966945337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.1966945337 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.1421595864
Short name T404
Test name
Test status
Simulation time 6741620363 ps
CPU time 141.44 seconds
Started Mar 19 01:06:40 PM PDT 24
Finished Mar 19 01:09:02 PM PDT 24
Peak memory 231268 kb
Host smart-2e1f3449-7e02-4eab-b860-d23d9f67114d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421595864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1421595864 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.643723665
Short name T891
Test name
Test status
Simulation time 1298661433 ps
CPU time 11.33 seconds
Started Mar 19 01:06:40 PM PDT 24
Finished Mar 19 01:06:51 PM PDT 24
Peak memory 218988 kb
Host smart-ef8aef0e-05de-457d-9dcc-e9cf0afcf44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643723665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.643723665 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.846641431
Short name T682
Test name
Test status
Simulation time 126162501949 ps
CPU time 812.98 seconds
Started Mar 19 01:06:50 PM PDT 24
Finished Mar 19 01:20:25 PM PDT 24
Peak memory 322488 kb
Host smart-b11ce8dd-2267-49d6-b1aa-4413b2953a29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=846641431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.846641431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.2097743989
Short name T805
Test name
Test status
Simulation time 1298952739 ps
CPU time 5.56 seconds
Started Mar 19 01:06:51 PM PDT 24
Finished Mar 19 01:06:57 PM PDT 24
Peak memory 215968 kb
Host smart-511633c6-4f7d-4d48-a68c-6b3ab26f0d99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097743989 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.kmac_test_vectors_kmac.2097743989 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.4078662765
Short name T614
Test name
Test status
Simulation time 183102774 ps
CPU time 4.62 seconds
Started Mar 19 01:06:49 PM PDT 24
Finished Mar 19 01:06:54 PM PDT 24
Peak memory 215948 kb
Host smart-3e1256a4-8ba6-4e8f-abaf-a7f45a2a068c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078662765 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.kmac_test_vectors_kmac_xof.4078662765 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.3609632391
Short name T1016
Test name
Test status
Simulation time 18543487401 ps
CPU time 1446.02 seconds
Started Mar 19 01:06:44 PM PDT 24
Finished Mar 19 01:30:50 PM PDT 24
Peak memory 379132 kb
Host smart-55bdce5f-d536-4d6c-bb9a-2fe704010c8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3609632391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.3609632391 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.4007764168
Short name T686
Test name
Test status
Simulation time 93031871555 ps
CPU time 1795.86 seconds
Started Mar 19 01:06:44 PM PDT 24
Finished Mar 19 01:36:40 PM PDT 24
Peak memory 368956 kb
Host smart-dae2e593-bfd8-47cb-b75a-2847d0b281d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4007764168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.4007764168 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.3473103724
Short name T831
Test name
Test status
Simulation time 47473342318 ps
CPU time 1307.06 seconds
Started Mar 19 01:06:46 PM PDT 24
Finished Mar 19 01:28:35 PM PDT 24
Peak memory 338616 kb
Host smart-ebed34c6-8af2-4ead-a240-e04d7a1385c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3473103724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.3473103724 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.4008602990
Short name T16
Test name
Test status
Simulation time 33416371305 ps
CPU time 863.12 seconds
Started Mar 19 01:06:51 PM PDT 24
Finished Mar 19 01:21:15 PM PDT 24
Peak memory 295784 kb
Host smart-142ae825-62d7-4dc2-b4bf-10553d6d6066
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4008602990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.4008602990 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.2091018596
Short name T836
Test name
Test status
Simulation time 231744105406 ps
CPU time 5138.19 seconds
Started Mar 19 01:06:48 PM PDT 24
Finished Mar 19 02:32:28 PM PDT 24
Peak memory 669592 kb
Host smart-8e89a331-db14-414c-96d4-4d7632ade89f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2091018596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.2091018596 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.2129700285
Short name T484
Test name
Test status
Simulation time 198783622604 ps
CPU time 4179.72 seconds
Started Mar 19 01:06:47 PM PDT 24
Finished Mar 19 02:16:28 PM PDT 24
Peak memory 573824 kb
Host smart-2eeaf052-597c-4212-8fa5-1d17c57e96bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2129700285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.2129700285 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.1351300141
Short name T645
Test name
Test status
Simulation time 106500291 ps
CPU time 0.76 seconds
Started Mar 19 01:06:58 PM PDT 24
Finished Mar 19 01:06:59 PM PDT 24
Peak memory 205332 kb
Host smart-cc55c23e-24a9-4de1-9d98-06061b002225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351300141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1351300141 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.1700500041
Short name T730
Test name
Test status
Simulation time 8767465393 ps
CPU time 158.98 seconds
Started Mar 19 01:06:58 PM PDT 24
Finished Mar 19 01:09:37 PM PDT 24
Peak memory 235152 kb
Host smart-68ce220e-0b4d-490b-9957-67931726a6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700500041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1700500041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.4015238696
Short name T783
Test name
Test status
Simulation time 8255781056 ps
CPU time 689.14 seconds
Started Mar 19 01:06:58 PM PDT 24
Finished Mar 19 01:18:27 PM PDT 24
Peak memory 232588 kb
Host smart-d51b0938-9c40-4c33-a98c-e03f77db79a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015238696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.4015238696 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.2923832868
Short name T593
Test name
Test status
Simulation time 7012821651 ps
CPU time 256.79 seconds
Started Mar 19 01:06:58 PM PDT 24
Finished Mar 19 01:11:15 PM PDT 24
Peak memory 244348 kb
Host smart-d31d7295-d9f4-4687-ab77-d4777765714f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923832868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2923832868 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.3370914092
Short name T801
Test name
Test status
Simulation time 6435159958 ps
CPU time 131.22 seconds
Started Mar 19 01:06:59 PM PDT 24
Finished Mar 19 01:09:11 PM PDT 24
Peak memory 240080 kb
Host smart-989d71d4-2ba0-4975-be86-e5047d1de213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370914092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.3370914092 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.4271355018
Short name T60
Test name
Test status
Simulation time 1539003360 ps
CPU time 4.41 seconds
Started Mar 19 01:07:02 PM PDT 24
Finished Mar 19 01:07:07 PM PDT 24
Peak memory 207520 kb
Host smart-64a35885-61c1-4c4d-93e2-cc7603765f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271355018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.4271355018 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.3182228633
Short name T507
Test name
Test status
Simulation time 44670162 ps
CPU time 1.41 seconds
Started Mar 19 01:06:58 PM PDT 24
Finished Mar 19 01:06:59 PM PDT 24
Peak memory 217116 kb
Host smart-e0ee441f-6f35-40b1-8d75-a4ee5d693830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182228633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.3182228633 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.1789782476
Short name T393
Test name
Test status
Simulation time 88299991010 ps
CPU time 2323.21 seconds
Started Mar 19 01:06:50 PM PDT 24
Finished Mar 19 01:45:35 PM PDT 24
Peak memory 455704 kb
Host smart-0dc19997-c4a5-440e-a759-ff3e888f8c7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789782476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.1789782476 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.543448598
Short name T710
Test name
Test status
Simulation time 3442277821 ps
CPU time 248.36 seconds
Started Mar 19 01:06:48 PM PDT 24
Finished Mar 19 01:10:57 PM PDT 24
Peak memory 243852 kb
Host smart-59cd162b-bbf5-48b7-a536-3a63bb866926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543448598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.543448598 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.736546192
Short name T578
Test name
Test status
Simulation time 1383435014 ps
CPU time 6.59 seconds
Started Mar 19 01:06:46 PM PDT 24
Finished Mar 19 01:06:54 PM PDT 24
Peak memory 219004 kb
Host smart-5d9af8f2-86cf-4492-b6e9-27b526656c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736546192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.736546192 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.178741092
Short name T325
Test name
Test status
Simulation time 376240664193 ps
CPU time 1128.45 seconds
Started Mar 19 01:06:57 PM PDT 24
Finished Mar 19 01:25:46 PM PDT 24
Peak memory 355500 kb
Host smart-ad690fd8-614c-432c-aced-5398c4eab574
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=178741092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.178741092 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.523042099
Short name T187
Test name
Test status
Simulation time 67309419 ps
CPU time 4.24 seconds
Started Mar 19 01:06:59 PM PDT 24
Finished Mar 19 01:07:04 PM PDT 24
Peak memory 215920 kb
Host smart-8cfef598-e845-43a6-b034-df5e2c56c839
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523042099 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.kmac_test_vectors_kmac.523042099 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.1014315467
Short name T961
Test name
Test status
Simulation time 276139165 ps
CPU time 4.43 seconds
Started Mar 19 01:06:57 PM PDT 24
Finished Mar 19 01:07:01 PM PDT 24
Peak memory 215968 kb
Host smart-f402800a-3fac-4c75-8407-5357c6d17b60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014315467 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.1014315467 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.3938636392
Short name T1000
Test name
Test status
Simulation time 401623742953 ps
CPU time 1924.36 seconds
Started Mar 19 01:07:01 PM PDT 24
Finished Mar 19 01:39:08 PM PDT 24
Peak memory 389096 kb
Host smart-dfcae3ac-e176-4b16-a089-6bdd017d6185
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3938636392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.3938636392 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.687412639
Short name T432
Test name
Test status
Simulation time 1009902685620 ps
CPU time 1710.46 seconds
Started Mar 19 01:07:00 PM PDT 24
Finished Mar 19 01:35:32 PM PDT 24
Peak memory 371156 kb
Host smart-26c4e6e2-9182-4bc4-b209-7a3d8e2113a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=687412639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.687412639 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.3785015084
Short name T599
Test name
Test status
Simulation time 60102015653 ps
CPU time 1345.14 seconds
Started Mar 19 01:06:58 PM PDT 24
Finished Mar 19 01:29:24 PM PDT 24
Peak memory 331824 kb
Host smart-5dd551ad-896f-436c-8d98-456bb81f5cd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3785015084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.3785015084 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.3004735212
Short name T1070
Test name
Test status
Simulation time 39945532733 ps
CPU time 796.93 seconds
Started Mar 19 01:07:00 PM PDT 24
Finished Mar 19 01:20:17 PM PDT 24
Peak memory 297176 kb
Host smart-27ea0d8e-9781-4384-aa5f-757dba8de73b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3004735212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.3004735212 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.1697403998
Short name T708
Test name
Test status
Simulation time 264358812086 ps
CPU time 5100.43 seconds
Started Mar 19 01:06:59 PM PDT 24
Finished Mar 19 02:32:00 PM PDT 24
Peak memory 649072 kb
Host smart-7df0c14c-377b-47bf-ba01-8a98f0949b19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1697403998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.1697403998 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.180247163
Short name T132
Test name
Test status
Simulation time 174716215206 ps
CPU time 3553.67 seconds
Started Mar 19 01:06:58 PM PDT 24
Finished Mar 19 02:06:12 PM PDT 24
Peak memory 571828 kb
Host smart-115c5da0-daef-4c3e-8fba-18fa2b113d54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=180247163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.180247163 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.792701590
Short name T315
Test name
Test status
Simulation time 17667827 ps
CPU time 0.76 seconds
Started Mar 19 01:03:47 PM PDT 24
Finished Mar 19 01:03:49 PM PDT 24
Peak memory 205400 kb
Host smart-e8325bdd-ec8e-4b54-86bc-3982c214feff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792701590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.792701590 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.2968832007
Short name T620
Test name
Test status
Simulation time 4512190148 ps
CPU time 42.68 seconds
Started Mar 19 01:03:48 PM PDT 24
Finished Mar 19 01:04:31 PM PDT 24
Peak memory 221232 kb
Host smart-80d03043-9491-4205-8d0c-77edebbb4685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968832007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2968832007 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.138829238
Short name T760
Test name
Test status
Simulation time 8482191591 ps
CPU time 41.53 seconds
Started Mar 19 01:03:48 PM PDT 24
Finished Mar 19 01:04:30 PM PDT 24
Peak memory 222684 kb
Host smart-a6eb6e7d-4bc2-4c26-99a9-1ee7e4d42da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138829238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.138829238 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.1550418834
Short name T141
Test name
Test status
Simulation time 18287123244 ps
CPU time 456.42 seconds
Started Mar 19 01:03:48 PM PDT 24
Finished Mar 19 01:11:25 PM PDT 24
Peak memory 229288 kb
Host smart-6558fab6-a4a5-4431-8331-701bcf2d72a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550418834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.1550418834 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.1427512084
Short name T337
Test name
Test status
Simulation time 3128894168 ps
CPU time 19.4 seconds
Started Mar 19 01:03:49 PM PDT 24
Finished Mar 19 01:04:09 PM PDT 24
Peak memory 223892 kb
Host smart-24ad30a0-0b98-436d-ae94-cb3e86a8aef2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1427512084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.1427512084 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.991304706
Short name T366
Test name
Test status
Simulation time 2556426113 ps
CPU time 14.79 seconds
Started Mar 19 01:03:46 PM PDT 24
Finished Mar 19 01:04:01 PM PDT 24
Peak memory 218400 kb
Host smart-15630726-5575-431f-8739-f17aa3546925
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=991304706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.991304706 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.366100364
Short name T835
Test name
Test status
Simulation time 50258500893 ps
CPU time 181.88 seconds
Started Mar 19 01:04:00 PM PDT 24
Finished Mar 19 01:07:02 PM PDT 24
Peak memory 236756 kb
Host smart-a599aca8-5de3-4516-b0e7-310b7effa80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366100364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.366100364 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.318079894
Short name T574
Test name
Test status
Simulation time 14290948062 ps
CPU time 242.3 seconds
Started Mar 19 01:03:51 PM PDT 24
Finished Mar 19 01:07:54 PM PDT 24
Peak memory 249296 kb
Host smart-01e2961a-3b13-4357-a012-e5114f44fcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318079894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.318079894 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.4052357738
Short name T802
Test name
Test status
Simulation time 412344530 ps
CPU time 1.08 seconds
Started Mar 19 01:03:47 PM PDT 24
Finished Mar 19 01:03:50 PM PDT 24
Peak memory 205892 kb
Host smart-51b7a480-890e-4785-bb37-50f4e4afa097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052357738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.4052357738 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.967763694
Short name T8
Test name
Test status
Simulation time 57296227 ps
CPU time 1.3 seconds
Started Mar 19 01:03:47 PM PDT 24
Finished Mar 19 01:03:50 PM PDT 24
Peak memory 215960 kb
Host smart-3baa5e9d-210b-4ca3-ae55-34f5d1166d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967763694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.967763694 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.4051312090
Short name T930
Test name
Test status
Simulation time 27128638988 ps
CPU time 1157.67 seconds
Started Mar 19 01:03:50 PM PDT 24
Finished Mar 19 01:23:09 PM PDT 24
Peak memory 345776 kb
Host smart-fb92220e-66cd-4fd2-8785-b62b226988e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051312090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.4051312090 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.3430854215
Short name T149
Test name
Test status
Simulation time 1822842109 ps
CPU time 82.78 seconds
Started Mar 19 01:03:47 PM PDT 24
Finished Mar 19 01:05:11 PM PDT 24
Peak memory 229596 kb
Host smart-01de8818-aa93-4529-bd57-f058437e424f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430854215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.3430854215 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.2969017291
Short name T71
Test name
Test status
Simulation time 6403503988 ps
CPU time 54.42 seconds
Started Mar 19 01:03:48 PM PDT 24
Finished Mar 19 01:04:43 PM PDT 24
Peak memory 252300 kb
Host smart-be1867ce-a277-4e0f-8388-4743e955ed2c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969017291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.2969017291 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.522282100
Short name T807
Test name
Test status
Simulation time 21712713627 ps
CPU time 193.7 seconds
Started Mar 19 01:03:52 PM PDT 24
Finished Mar 19 01:07:07 PM PDT 24
Peak memory 236696 kb
Host smart-a1e54f29-9026-488c-93e4-07ed7c028f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522282100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.522282100 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.1897107425
Short name T262
Test name
Test status
Simulation time 2627894057 ps
CPU time 15.9 seconds
Started Mar 19 01:03:50 PM PDT 24
Finished Mar 19 01:04:07 PM PDT 24
Peak memory 219296 kb
Host smart-1cfc5616-a2e8-4ae3-9d67-095a3af6f4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897107425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.1897107425 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.4041742712
Short name T437
Test name
Test status
Simulation time 50045080692 ps
CPU time 1299.18 seconds
Started Mar 19 01:04:01 PM PDT 24
Finished Mar 19 01:25:40 PM PDT 24
Peak memory 337772 kb
Host smart-38f11a69-a6aa-4b61-978e-dc94ca299ee7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4041742712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.4041742712 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.3291143836
Short name T377
Test name
Test status
Simulation time 247863952 ps
CPU time 4.89 seconds
Started Mar 19 01:03:51 PM PDT 24
Finished Mar 19 01:03:56 PM PDT 24
Peak memory 215908 kb
Host smart-1b8d1c8d-20f2-449e-8619-690cc9f748e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291143836 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.3291143836 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.3185228166
Short name T996
Test name
Test status
Simulation time 1044819674 ps
CPU time 4.74 seconds
Started Mar 19 01:03:59 PM PDT 24
Finished Mar 19 01:04:04 PM PDT 24
Peak memory 215860 kb
Host smart-0f241211-2236-4d57-b75d-2ba3c8c7ba15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185228166 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.3185228166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.2706564049
Short name T1055
Test name
Test status
Simulation time 68727146318 ps
CPU time 1811.08 seconds
Started Mar 19 01:03:48 PM PDT 24
Finished Mar 19 01:34:00 PM PDT 24
Peak memory 398872 kb
Host smart-dc242ef4-2da4-4bb1-b267-0e75bb50e115
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2706564049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.2706564049 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.3629031718
Short name T294
Test name
Test status
Simulation time 98018258907 ps
CPU time 1572.01 seconds
Started Mar 19 01:03:52 PM PDT 24
Finished Mar 19 01:30:05 PM PDT 24
Peak memory 372948 kb
Host smart-b68fb9b2-ea72-48b5-985a-25295230e141
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3629031718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3629031718 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.586931225
Short name T463
Test name
Test status
Simulation time 14195046355 ps
CPU time 1160.4 seconds
Started Mar 19 01:04:00 PM PDT 24
Finished Mar 19 01:23:21 PM PDT 24
Peak memory 334540 kb
Host smart-c330bbf3-917c-445d-8a59-3e7b18690d7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=586931225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.586931225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.3461298233
Short name T664
Test name
Test status
Simulation time 9524024370 ps
CPU time 770.73 seconds
Started Mar 19 01:03:52 PM PDT 24
Finished Mar 19 01:16:44 PM PDT 24
Peak memory 294748 kb
Host smart-9ba600b2-961f-409b-80b8-ff66ed326282
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3461298233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3461298233 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.42889498
Short name T248
Test name
Test status
Simulation time 637424665923 ps
CPU time 4308.36 seconds
Started Mar 19 01:03:51 PM PDT 24
Finished Mar 19 02:15:41 PM PDT 24
Peak memory 653376 kb
Host smart-2de3eeec-4884-4c02-9c39-9c2d9fd3b2ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=42889498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.42889498 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.794726108
Short name T216
Test name
Test status
Simulation time 185247764144 ps
CPU time 3996.02 seconds
Started Mar 19 01:03:46 PM PDT 24
Finished Mar 19 02:10:23 PM PDT 24
Peak memory 548168 kb
Host smart-27835bff-6196-49c6-874a-0a1c0fbcd8de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=794726108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.794726108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.1406824166
Short name T845
Test name
Test status
Simulation time 32602491 ps
CPU time 0.82 seconds
Started Mar 19 01:07:18 PM PDT 24
Finished Mar 19 01:07:19 PM PDT 24
Peak memory 205336 kb
Host smart-1d020e3c-886a-444f-8677-6bc5855bc783
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406824166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.1406824166 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.2119482940
Short name T605
Test name
Test status
Simulation time 5309499393 ps
CPU time 130.32 seconds
Started Mar 19 01:07:07 PM PDT 24
Finished Mar 19 01:09:17 PM PDT 24
Peak memory 233540 kb
Host smart-f4994539-c981-4d2c-bbb8-a1826899b559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119482940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.2119482940 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.165014377
Short name T638
Test name
Test status
Simulation time 4598818364 ps
CPU time 170.83 seconds
Started Mar 19 01:07:16 PM PDT 24
Finished Mar 19 01:10:09 PM PDT 24
Peak memory 239688 kb
Host smart-b6118f66-0adb-4cdd-8333-fc595f89af49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165014377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.165014377 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.1537698634
Short name T893
Test name
Test status
Simulation time 8268605675 ps
CPU time 220.87 seconds
Started Mar 19 01:07:21 PM PDT 24
Finished Mar 19 01:11:02 PM PDT 24
Peak memory 248728 kb
Host smart-8b4cee31-2942-4550-a997-9512920513be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537698634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.1537698634 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.2397516399
Short name T349
Test name
Test status
Simulation time 1360989698 ps
CPU time 4.05 seconds
Started Mar 19 01:07:17 PM PDT 24
Finished Mar 19 01:07:22 PM PDT 24
Peak memory 207576 kb
Host smart-76197ff4-cc4d-44e9-9240-38e771557544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397516399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2397516399 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.867907250
Short name T446
Test name
Test status
Simulation time 63496404 ps
CPU time 1.26 seconds
Started Mar 19 01:07:16 PM PDT 24
Finished Mar 19 01:07:17 PM PDT 24
Peak memory 215848 kb
Host smart-28ad40cf-b57a-4427-a626-aff8a85a24b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867907250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.867907250 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.1166556167
Short name T239
Test name
Test status
Simulation time 114104422268 ps
CPU time 2087.83 seconds
Started Mar 19 01:07:08 PM PDT 24
Finished Mar 19 01:41:57 PM PDT 24
Peak memory 439540 kb
Host smart-ba96eb31-b6ac-49c6-913b-84121d29d8ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166556167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.1166556167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.88993467
Short name T886
Test name
Test status
Simulation time 5019531491 ps
CPU time 190.29 seconds
Started Mar 19 01:07:08 PM PDT 24
Finished Mar 19 01:10:19 PM PDT 24
Peak memory 237908 kb
Host smart-0ad4fcbd-4b95-4e71-9f78-ee8ed5595b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88993467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.88993467 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.2477766107
Short name T479
Test name
Test status
Simulation time 3967204273 ps
CPU time 49.67 seconds
Started Mar 19 01:07:06 PM PDT 24
Finished Mar 19 01:07:56 PM PDT 24
Peak memory 221864 kb
Host smart-7ef1ac4a-69e7-4553-95c5-a50be54c4380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477766107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2477766107 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.1449207293
Short name T859
Test name
Test status
Simulation time 3704422906 ps
CPU time 82.95 seconds
Started Mar 19 01:07:17 PM PDT 24
Finished Mar 19 01:08:41 PM PDT 24
Peak memory 240504 kb
Host smart-3159bf3b-d55d-40f1-ac7c-247aa43745fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1449207293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1449207293 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.4140679727
Short name T433
Test name
Test status
Simulation time 168255260 ps
CPU time 4.7 seconds
Started Mar 19 01:07:07 PM PDT 24
Finished Mar 19 01:07:12 PM PDT 24
Peak memory 215936 kb
Host smart-df23e21d-8a3e-450b-b89d-81fb5d7f1a43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140679727 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.kmac_test_vectors_kmac.4140679727 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.2641928655
Short name T687
Test name
Test status
Simulation time 266943441 ps
CPU time 5.09 seconds
Started Mar 19 01:07:09 PM PDT 24
Finished Mar 19 01:07:14 PM PDT 24
Peak memory 216016 kb
Host smart-731ee049-727c-4515-baa2-8bcf608daf8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641928655 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.kmac_test_vectors_kmac_xof.2641928655 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.2434020189
Short name T741
Test name
Test status
Simulation time 136340863737 ps
CPU time 1821.9 seconds
Started Mar 19 01:07:06 PM PDT 24
Finished Mar 19 01:37:29 PM PDT 24
Peak memory 387548 kb
Host smart-ae072312-3779-4b2e-bb45-8b8dcb3f8280
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2434020189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.2434020189 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.2622152655
Short name T816
Test name
Test status
Simulation time 70778279334 ps
CPU time 1785.62 seconds
Started Mar 19 01:07:07 PM PDT 24
Finished Mar 19 01:36:53 PM PDT 24
Peak memory 372860 kb
Host smart-aafb424f-6907-4dfb-897b-b5ebc5fdc4a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2622152655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.2622152655 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.1251987484
Short name T550
Test name
Test status
Simulation time 125939172476 ps
CPU time 1387.1 seconds
Started Mar 19 01:07:06 PM PDT 24
Finished Mar 19 01:30:14 PM PDT 24
Peak memory 333016 kb
Host smart-bf895e20-9bbd-4b6b-9d04-8ce10e204885
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1251987484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.1251987484 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.1486381595
Short name T66
Test name
Test status
Simulation time 130345190007 ps
CPU time 938.27 seconds
Started Mar 19 01:07:08 PM PDT 24
Finished Mar 19 01:22:47 PM PDT 24
Peak memory 295140 kb
Host smart-a0362417-4958-4f84-8b55-f73c290935dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1486381595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.1486381595 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.2772693189
Short name T442
Test name
Test status
Simulation time 362395745907 ps
CPU time 4006.54 seconds
Started Mar 19 01:07:08 PM PDT 24
Finished Mar 19 02:13:56 PM PDT 24
Peak memory 646972 kb
Host smart-0075b5e6-f8b2-4945-afdb-0f2d792614e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2772693189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.2772693189 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.1092483670
Short name T282
Test name
Test status
Simulation time 540494344212 ps
CPU time 4099.63 seconds
Started Mar 19 01:07:09 PM PDT 24
Finished Mar 19 02:15:29 PM PDT 24
Peak memory 564924 kb
Host smart-b4480017-78f4-4f06-9934-1fd0a610f08d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1092483670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.1092483670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.1100316522
Short name T502
Test name
Test status
Simulation time 33195344 ps
CPU time 0.8 seconds
Started Mar 19 01:07:31 PM PDT 24
Finished Mar 19 01:07:31 PM PDT 24
Peak memory 205392 kb
Host smart-cdf4213a-a80a-496f-b0b2-c75477348dcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100316522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1100316522 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.3876874078
Short name T341
Test name
Test status
Simulation time 3517328731 ps
CPU time 58.95 seconds
Started Mar 19 01:07:32 PM PDT 24
Finished Mar 19 01:08:31 PM PDT 24
Peak memory 225132 kb
Host smart-a3c82e4c-e2f4-40c4-be74-9cc5435188b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876874078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3876874078 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.2384844728
Short name T1050
Test name
Test status
Simulation time 24330830451 ps
CPU time 772.65 seconds
Started Mar 19 01:07:17 PM PDT 24
Finished Mar 19 01:20:11 PM PDT 24
Peak memory 232344 kb
Host smart-43dac18a-262c-417b-b8fd-e65491431305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384844728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.2384844728 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.2809777217
Short name T558
Test name
Test status
Simulation time 53396213085 ps
CPU time 267.43 seconds
Started Mar 19 01:07:31 PM PDT 24
Finished Mar 19 01:11:59 PM PDT 24
Peak memory 240664 kb
Host smart-dcb07cbe-4dd3-4f7b-9b19-29be649397a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809777217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.2809777217 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.4243737498
Short name T32
Test name
Test status
Simulation time 6859377149 ps
CPU time 139.78 seconds
Started Mar 19 01:07:32 PM PDT 24
Finished Mar 19 01:09:52 PM PDT 24
Peak memory 252044 kb
Host smart-eb109917-a559-4e29-8640-ce93b2bca45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243737498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.4243737498 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.461312038
Short name T321
Test name
Test status
Simulation time 360519406 ps
CPU time 1.3 seconds
Started Mar 19 01:07:32 PM PDT 24
Finished Mar 19 01:07:33 PM PDT 24
Peak memory 206028 kb
Host smart-2fb189ce-e215-4afc-b389-acf42ff85b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461312038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.461312038 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.1150478267
Short name T38
Test name
Test status
Simulation time 36087771 ps
CPU time 1.36 seconds
Started Mar 19 01:07:32 PM PDT 24
Finished Mar 19 01:07:34 PM PDT 24
Peak memory 217240 kb
Host smart-b6801aba-9e44-49bf-bff5-70e0893c969d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150478267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1150478267 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.2603640961
Short name T211
Test name
Test status
Simulation time 68780520968 ps
CPU time 1967.39 seconds
Started Mar 19 01:07:16 PM PDT 24
Finished Mar 19 01:40:05 PM PDT 24
Peak memory 418024 kb
Host smart-f4f61a08-89f4-4d4d-9f34-19b92a7697ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603640961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.2603640961 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_smoke.1091519141
Short name T790
Test name
Test status
Simulation time 874216450 ps
CPU time 23.76 seconds
Started Mar 19 01:07:19 PM PDT 24
Finished Mar 19 01:07:43 PM PDT 24
Peak memory 217516 kb
Host smart-c2e9a403-5d6a-48b2-b686-23dd1283c583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091519141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.1091519141 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.499713229
Short name T985
Test name
Test status
Simulation time 66884101182 ps
CPU time 1314.48 seconds
Started Mar 19 01:07:33 PM PDT 24
Finished Mar 19 01:29:28 PM PDT 24
Peak memory 355228 kb
Host smart-3d8eb93e-8275-4683-adba-929a269e2364
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=499713229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.499713229 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.1633858754
Short name T199
Test name
Test status
Simulation time 316639151 ps
CPU time 4.26 seconds
Started Mar 19 01:07:17 PM PDT 24
Finished Mar 19 01:07:22 PM PDT 24
Peak memory 215872 kb
Host smart-b8d27f9f-6858-4db8-b650-3ef07bd93379
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633858754 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.1633858754 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.3179390623
Short name T660
Test name
Test status
Simulation time 273000038 ps
CPU time 3.9 seconds
Started Mar 19 01:07:31 PM PDT 24
Finished Mar 19 01:07:36 PM PDT 24
Peak memory 209472 kb
Host smart-9cebb4fe-cc56-484a-83ce-1056bb961e54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179390623 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.kmac_test_vectors_kmac_xof.3179390623 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.11453421
Short name T673
Test name
Test status
Simulation time 91713127523 ps
CPU time 1621.4 seconds
Started Mar 19 01:07:17 PM PDT 24
Finished Mar 19 01:34:20 PM PDT 24
Peak memory 400648 kb
Host smart-4167d5f3-f490-4879-972c-a3f616643673
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=11453421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.11453421 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.3728120330
Short name T892
Test name
Test status
Simulation time 18646973440 ps
CPU time 1557.45 seconds
Started Mar 19 01:07:17 PM PDT 24
Finished Mar 19 01:33:15 PM PDT 24
Peak memory 378048 kb
Host smart-d2e97e7a-59a6-4b46-a48a-30568bfb9b5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3728120330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.3728120330 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.4150518743
Short name T735
Test name
Test status
Simulation time 14517248411 ps
CPU time 1044.43 seconds
Started Mar 19 01:07:17 PM PDT 24
Finished Mar 19 01:24:42 PM PDT 24
Peak memory 334652 kb
Host smart-a851357d-5d6d-4a88-84fd-9ed56271f446
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4150518743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.4150518743 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.1062039112
Short name T131
Test name
Test status
Simulation time 43986519755 ps
CPU time 818.26 seconds
Started Mar 19 01:07:17 PM PDT 24
Finished Mar 19 01:20:56 PM PDT 24
Peak memory 298028 kb
Host smart-0a024aaa-50a4-4c27-9de1-10e740e3ce6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1062039112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.1062039112 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.2794338367
Short name T526
Test name
Test status
Simulation time 565151852780 ps
CPU time 5372.19 seconds
Started Mar 19 01:07:17 PM PDT 24
Finished Mar 19 02:36:51 PM PDT 24
Peak memory 663228 kb
Host smart-475d4a22-d356-4235-844c-f71b83d3d480
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2794338367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.2794338367 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.864978623
Short name T358
Test name
Test status
Simulation time 929852973089 ps
CPU time 4505.86 seconds
Started Mar 19 01:07:15 PM PDT 24
Finished Mar 19 02:22:22 PM PDT 24
Peak memory 550704 kb
Host smart-5515de11-2585-49e4-9d7e-0cf2831fb5ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=864978623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.864978623 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.318991943
Short name T448
Test name
Test status
Simulation time 94216000 ps
CPU time 0.72 seconds
Started Mar 19 01:07:45 PM PDT 24
Finished Mar 19 01:07:46 PM PDT 24
Peak memory 205288 kb
Host smart-db2e22c5-22e2-4a6b-a412-e71bb2cf53eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318991943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.318991943 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.2106937356
Short name T320
Test name
Test status
Simulation time 47526520167 ps
CPU time 300.13 seconds
Started Mar 19 01:07:46 PM PDT 24
Finished Mar 19 01:12:47 PM PDT 24
Peak memory 246600 kb
Host smart-abfd0a54-2a7e-4ee4-ba0b-d482e8721f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106937356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.2106937356 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.2950423889
Short name T527
Test name
Test status
Simulation time 8737270725 ps
CPU time 183.41 seconds
Started Mar 19 01:07:36 PM PDT 24
Finished Mar 19 01:10:40 PM PDT 24
Peak memory 224248 kb
Host smart-bbed2389-c1d2-4192-9aef-5481310c9ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950423889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.2950423889 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_error.1511695392
Short name T823
Test name
Test status
Simulation time 14559100694 ps
CPU time 381.03 seconds
Started Mar 19 01:07:45 PM PDT 24
Finished Mar 19 01:14:06 PM PDT 24
Peak memory 256832 kb
Host smart-e688d6c7-2110-469a-b03e-1a3b6a04cb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511695392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.1511695392 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.4223313706
Short name T520
Test name
Test status
Simulation time 3973882763 ps
CPU time 21.97 seconds
Started Mar 19 01:07:47 PM PDT 24
Finished Mar 19 01:08:09 PM PDT 24
Peak memory 232408 kb
Host smart-af82fe06-7fb6-42d3-99d9-8a21efacfe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223313706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.4223313706 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.637947451
Short name T782
Test name
Test status
Simulation time 13978981331 ps
CPU time 139.73 seconds
Started Mar 19 01:07:30 PM PDT 24
Finished Mar 19 01:09:50 PM PDT 24
Peak memory 229036 kb
Host smart-0646244e-226b-4695-b213-3219d58371f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637947451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_an
d_output.637947451 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.3770962295
Short name T277
Test name
Test status
Simulation time 51796055085 ps
CPU time 321.12 seconds
Started Mar 19 01:07:31 PM PDT 24
Finished Mar 19 01:12:53 PM PDT 24
Peak memory 242380 kb
Host smart-b4cfa7c9-f82b-4e02-85c8-4ec904fece8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770962295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.3770962295 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.1616106154
Short name T493
Test name
Test status
Simulation time 2064227357 ps
CPU time 44.06 seconds
Started Mar 19 01:07:31 PM PDT 24
Finished Mar 19 01:08:15 PM PDT 24
Peak memory 215956 kb
Host smart-4f4381b7-f242-4cf2-ba31-77019dfa479c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616106154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.1616106154 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.1689557107
Short name T504
Test name
Test status
Simulation time 8959936918 ps
CPU time 189.87 seconds
Started Mar 19 01:07:45 PM PDT 24
Finished Mar 19 01:10:55 PM PDT 24
Peak memory 240568 kb
Host smart-30d8bfa1-981b-4b45-b28b-c9768914d7a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1689557107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.1689557107 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.2517354299
Short name T732
Test name
Test status
Simulation time 673833921 ps
CPU time 5.12 seconds
Started Mar 19 01:07:32 PM PDT 24
Finished Mar 19 01:07:37 PM PDT 24
Peak memory 215908 kb
Host smart-34626fd4-d9e4-4540-868a-ca1d43daef80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517354299 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.2517354299 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.3024745064
Short name T306
Test name
Test status
Simulation time 975008152 ps
CPU time 5.35 seconds
Started Mar 19 01:07:46 PM PDT 24
Finished Mar 19 01:07:52 PM PDT 24
Peak memory 215992 kb
Host smart-9ae08375-5b16-42ab-9404-d776dcf663f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024745064 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.kmac_test_vectors_kmac_xof.3024745064 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.3322696565
Short name T130
Test name
Test status
Simulation time 128654400480 ps
CPU time 1887.33 seconds
Started Mar 19 01:07:32 PM PDT 24
Finished Mar 19 01:39:00 PM PDT 24
Peak memory 389228 kb
Host smart-4ada5327-c14e-4db8-93a1-9a8375655e2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3322696565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.3322696565 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.2768563853
Short name T848
Test name
Test status
Simulation time 192717995399 ps
CPU time 1909.97 seconds
Started Mar 19 01:07:32 PM PDT 24
Finished Mar 19 01:39:23 PM PDT 24
Peak memory 377128 kb
Host smart-22af9243-044e-4c1d-bd60-ac3f2932b148
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2768563853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.2768563853 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.54031152
Short name T249
Test name
Test status
Simulation time 637590778502 ps
CPU time 1443.85 seconds
Started Mar 19 01:07:31 PM PDT 24
Finished Mar 19 01:31:36 PM PDT 24
Peak memory 334336 kb
Host smart-0e8f6446-8b4b-4b86-93c7-f49cad9ae84a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=54031152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.54031152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.488816851
Short name T201
Test name
Test status
Simulation time 59864203613 ps
CPU time 984.15 seconds
Started Mar 19 01:07:32 PM PDT 24
Finished Mar 19 01:23:56 PM PDT 24
Peak memory 298488 kb
Host smart-56064a54-63c0-481f-b053-97322bc80413
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=488816851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.488816851 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.2304688799
Short name T681
Test name
Test status
Simulation time 51823558136 ps
CPU time 4175.84 seconds
Started Mar 19 01:07:32 PM PDT 24
Finished Mar 19 02:17:09 PM PDT 24
Peak memory 648136 kb
Host smart-28371445-1528-41a8-8869-97ba28f6cbc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2304688799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.2304688799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.2015445807
Short name T228
Test name
Test status
Simulation time 197194247388 ps
CPU time 4223.82 seconds
Started Mar 19 01:07:33 PM PDT 24
Finished Mar 19 02:17:57 PM PDT 24
Peak memory 566584 kb
Host smart-71aacde6-f54e-4fa3-b4d0-6739276361aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2015445807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.2015445807 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.244362403
Short name T608
Test name
Test status
Simulation time 21570727 ps
CPU time 0.81 seconds
Started Mar 19 01:07:57 PM PDT 24
Finished Mar 19 01:07:58 PM PDT 24
Peak memory 205344 kb
Host smart-7f68318c-ea13-444a-abb0-521c872a087d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244362403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.244362403 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.3039969439
Short name T152
Test name
Test status
Simulation time 8708352832 ps
CPU time 222.82 seconds
Started Mar 19 01:07:45 PM PDT 24
Finished Mar 19 01:11:28 PM PDT 24
Peak memory 243888 kb
Host smart-6b1ff7d3-d22e-4078-a11b-b18351414ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039969439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.3039969439 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.984586234
Short name T431
Test name
Test status
Simulation time 9939275733 ps
CPU time 275.76 seconds
Started Mar 19 01:07:45 PM PDT 24
Finished Mar 19 01:12:21 PM PDT 24
Peak memory 226608 kb
Host smart-a72fd69a-e2e9-4e2a-a990-982a99999faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984586234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.984586234 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.2401850851
Short name T770
Test name
Test status
Simulation time 23590936853 ps
CPU time 273.29 seconds
Started Mar 19 01:07:45 PM PDT 24
Finished Mar 19 01:12:19 PM PDT 24
Peak memory 243232 kb
Host smart-77eaba45-2cc8-40c3-b48b-e1b4e42916cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401850851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.2401850851 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.3008633525
Short name T629
Test name
Test status
Simulation time 4336758451 ps
CPU time 260.79 seconds
Started Mar 19 01:07:45 PM PDT 24
Finished Mar 19 01:12:07 PM PDT 24
Peak memory 256144 kb
Host smart-bb932be8-8d5e-4624-b2ad-6e896ab1d9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008633525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3008633525 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.1357797463
Short name T63
Test name
Test status
Simulation time 4548916763 ps
CPU time 5.49 seconds
Started Mar 19 01:07:47 PM PDT 24
Finished Mar 19 01:07:53 PM PDT 24
Peak memory 215748 kb
Host smart-a8920dd5-1eed-453f-9452-7b3da8587f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357797463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.1357797463 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.3922822465
Short name T844
Test name
Test status
Simulation time 475134313 ps
CPU time 1.58 seconds
Started Mar 19 01:07:48 PM PDT 24
Finished Mar 19 01:07:50 PM PDT 24
Peak memory 215824 kb
Host smart-35b91cfd-46ef-4af1-8646-a944e447c8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922822465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.3922822465 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.3252718614
Short name T669
Test name
Test status
Simulation time 81588212686 ps
CPU time 1965.16 seconds
Started Mar 19 01:07:47 PM PDT 24
Finished Mar 19 01:40:33 PM PDT 24
Peak memory 403492 kb
Host smart-d8aab1ca-7995-4d11-af5c-52f6e0b83872
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252718614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.3252718614 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.1105533388
Short name T953
Test name
Test status
Simulation time 62707336060 ps
CPU time 319.59 seconds
Started Mar 19 01:07:47 PM PDT 24
Finished Mar 19 01:13:07 PM PDT 24
Peak memory 244508 kb
Host smart-c79f7e19-8bf4-4a71-b5f9-2b9c3723d11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105533388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.1105533388 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.990906055
Short name T1082
Test name
Test status
Simulation time 859290729 ps
CPU time 44.67 seconds
Started Mar 19 01:07:46 PM PDT 24
Finished Mar 19 01:08:31 PM PDT 24
Peak memory 216960 kb
Host smart-e1b7062c-8142-42ea-b145-7322db442fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990906055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.990906055 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.3121230928
Short name T671
Test name
Test status
Simulation time 50901852246 ps
CPU time 547.44 seconds
Started Mar 19 01:07:46 PM PDT 24
Finished Mar 19 01:16:54 PM PDT 24
Peak memory 289808 kb
Host smart-3592ea3d-8cdf-449c-b970-d594968b88a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3121230928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.3121230928 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.1582749978
Short name T475
Test name
Test status
Simulation time 66234512 ps
CPU time 3.65 seconds
Started Mar 19 01:07:45 PM PDT 24
Finished Mar 19 01:07:49 PM PDT 24
Peak memory 215876 kb
Host smart-91c853ae-6a2f-40bf-9cb3-c06e51ba1dd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582749978 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.kmac_test_vectors_kmac.1582749978 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.1817551401
Short name T809
Test name
Test status
Simulation time 334600487 ps
CPU time 4.17 seconds
Started Mar 19 01:07:46 PM PDT 24
Finished Mar 19 01:07:51 PM PDT 24
Peak memory 215940 kb
Host smart-6b402bde-e16a-46b4-8408-96ad80223aaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817551401 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.1817551401 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.3273957135
Short name T665
Test name
Test status
Simulation time 196625307441 ps
CPU time 2028.3 seconds
Started Mar 19 01:07:46 PM PDT 24
Finished Mar 19 01:41:34 PM PDT 24
Peak memory 389588 kb
Host smart-e25004b2-b908-48d5-a9cd-a39be3986c09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3273957135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.3273957135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.499548377
Short name T881
Test name
Test status
Simulation time 24753178147 ps
CPU time 1433.81 seconds
Started Mar 19 01:07:47 PM PDT 24
Finished Mar 19 01:31:41 PM PDT 24
Peak memory 371176 kb
Host smart-b4b0917a-9713-4451-ad50-465848974011
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=499548377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.499548377 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.167998710
Short name T907
Test name
Test status
Simulation time 207736397941 ps
CPU time 1302.42 seconds
Started Mar 19 01:07:46 PM PDT 24
Finished Mar 19 01:29:29 PM PDT 24
Peak memory 328264 kb
Host smart-6ed88d33-4046-4a4a-94af-b83bb27a0385
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=167998710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.167998710 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.3626628984
Short name T685
Test name
Test status
Simulation time 32028770168 ps
CPU time 945.87 seconds
Started Mar 19 01:07:47 PM PDT 24
Finished Mar 19 01:23:33 PM PDT 24
Peak memory 291816 kb
Host smart-01e933fa-7ca3-4497-8008-d73aab2a9905
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3626628984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.3626628984 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.1921747524
Short name T380
Test name
Test status
Simulation time 52121539422 ps
CPU time 4151.85 seconds
Started Mar 19 01:07:47 PM PDT 24
Finished Mar 19 02:17:00 PM PDT 24
Peak memory 623684 kb
Host smart-dd57222e-1f52-4bde-99dd-5cc4c01db389
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1921747524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.1921747524 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.763752209
Short name T979
Test name
Test status
Simulation time 209360366112 ps
CPU time 3380.03 seconds
Started Mar 19 01:07:45 PM PDT 24
Finished Mar 19 02:04:06 PM PDT 24
Peak memory 575080 kb
Host smart-73dc5a36-b027-40d8-b8d4-390750450769
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=763752209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.763752209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.3919003248
Short name T488
Test name
Test status
Simulation time 43026952 ps
CPU time 0.8 seconds
Started Mar 19 01:07:56 PM PDT 24
Finished Mar 19 01:07:57 PM PDT 24
Peak memory 205304 kb
Host smart-ba26e2c1-346b-49b3-aee2-6f5184c5be5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919003248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3919003248 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.1331946448
Short name T77
Test name
Test status
Simulation time 955532562 ps
CPU time 20.42 seconds
Started Mar 19 01:08:01 PM PDT 24
Finished Mar 19 01:08:25 PM PDT 24
Peak memory 224128 kb
Host smart-ec0cc0a5-6246-423e-89fa-176b1cc45ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331946448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.1331946448 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.2572251551
Short name T176
Test name
Test status
Simulation time 38806816547 ps
CPU time 437.36 seconds
Started Mar 19 01:07:59 PM PDT 24
Finished Mar 19 01:15:16 PM PDT 24
Peak memory 229488 kb
Host smart-9f3c5a5d-49a1-47d0-af63-ee47cb30b6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572251551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.2572251551 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.2328628171
Short name T462
Test name
Test status
Simulation time 718525989 ps
CPU time 9.46 seconds
Started Mar 19 01:07:58 PM PDT 24
Finished Mar 19 01:08:08 PM PDT 24
Peak memory 215940 kb
Host smart-96aeca8c-6cbf-47be-8198-bb5a5621b0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328628171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2328628171 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.1986873620
Short name T853
Test name
Test status
Simulation time 8697231580 ps
CPU time 233.12 seconds
Started Mar 19 01:08:00 PM PDT 24
Finished Mar 19 01:11:53 PM PDT 24
Peak memory 256940 kb
Host smart-09aa9c06-de15-4268-b7e4-0ba79da03f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986873620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.1986873620 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.3839620048
Short name T20
Test name
Test status
Simulation time 4255282361 ps
CPU time 5.97 seconds
Started Mar 19 01:07:57 PM PDT 24
Finished Mar 19 01:08:03 PM PDT 24
Peak memory 207664 kb
Host smart-80cdb0e0-adbd-4d97-b677-f794eb2f700a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839620048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.3839620048 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.1970080365
Short name T1071
Test name
Test status
Simulation time 99661198 ps
CPU time 1.28 seconds
Started Mar 19 01:07:57 PM PDT 24
Finished Mar 19 01:07:59 PM PDT 24
Peak memory 216948 kb
Host smart-0cca9c7d-6122-4bdb-bb49-d3c374bb9ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970080365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1970080365 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.1327250265
Short name T868
Test name
Test status
Simulation time 103360069426 ps
CPU time 2232.1 seconds
Started Mar 19 01:07:58 PM PDT 24
Finished Mar 19 01:45:11 PM PDT 24
Peak memory 442988 kb
Host smart-23cc7d61-f94b-4051-a6a5-c70ac1355049
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327250265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.1327250265 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.1538742495
Short name T17
Test name
Test status
Simulation time 31575852350 ps
CPU time 198.71 seconds
Started Mar 19 01:07:59 PM PDT 24
Finished Mar 19 01:11:17 PM PDT 24
Peak memory 240572 kb
Host smart-33e3401c-86bb-447f-b6a6-0d60448fd7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538742495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.1538742495 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.3237293846
Short name T905
Test name
Test status
Simulation time 2996686010 ps
CPU time 26.47 seconds
Started Mar 19 01:08:00 PM PDT 24
Finished Mar 19 01:08:26 PM PDT 24
Peak memory 217224 kb
Host smart-17117470-f42e-4823-843f-930b016abea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237293846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.3237293846 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.2970081358
Short name T935
Test name
Test status
Simulation time 32362819915 ps
CPU time 578.46 seconds
Started Mar 19 01:08:01 PM PDT 24
Finished Mar 19 01:17:40 PM PDT 24
Peak memory 288712 kb
Host smart-cf50f8ea-c408-4c2c-b15d-0f5068de1066
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2970081358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.2970081358 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.3994857429
Short name T362
Test name
Test status
Simulation time 321815733 ps
CPU time 3.76 seconds
Started Mar 19 01:07:59 PM PDT 24
Finished Mar 19 01:08:03 PM PDT 24
Peak memory 208972 kb
Host smart-682ddc91-7bdc-42f8-ae59-a4fa7ea86846
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994857429 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.3994857429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.633518772
Short name T1019
Test name
Test status
Simulation time 752836806 ps
CPU time 5.51 seconds
Started Mar 19 01:08:04 PM PDT 24
Finished Mar 19 01:08:10 PM PDT 24
Peak memory 215948 kb
Host smart-f713eb14-5cfd-469c-89cb-1b03866b0afa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633518772 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.kmac_test_vectors_kmac_xof.633518772 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.312604949
Short name T588
Test name
Test status
Simulation time 247969102231 ps
CPU time 1926.43 seconds
Started Mar 19 01:07:57 PM PDT 24
Finished Mar 19 01:40:04 PM PDT 24
Peak memory 389488 kb
Host smart-d7a7bcfe-a0f6-4156-a065-5b2268ba69c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=312604949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.312604949 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.3878681140
Short name T516
Test name
Test status
Simulation time 657822292188 ps
CPU time 2069.64 seconds
Started Mar 19 01:07:57 PM PDT 24
Finished Mar 19 01:42:27 PM PDT 24
Peak memory 373248 kb
Host smart-8e5e1ea5-75f8-4026-8447-9581983b0b35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3878681140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.3878681140 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.517018379
Short name T402
Test name
Test status
Simulation time 1023744559907 ps
CPU time 1609.59 seconds
Started Mar 19 01:07:57 PM PDT 24
Finished Mar 19 01:34:47 PM PDT 24
Peak memory 336348 kb
Host smart-3e732b11-1737-4b48-9224-b4af4c79ae7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=517018379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.517018379 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.619155494
Short name T372
Test name
Test status
Simulation time 59983557020 ps
CPU time 888.01 seconds
Started Mar 19 01:07:58 PM PDT 24
Finished Mar 19 01:22:47 PM PDT 24
Peak memory 293848 kb
Host smart-a2d0adcc-6e7b-40df-9685-07b8891ffef4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=619155494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.619155494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.1037373748
Short name T508
Test name
Test status
Simulation time 212194956768 ps
CPU time 4307.73 seconds
Started Mar 19 01:07:56 PM PDT 24
Finished Mar 19 02:19:45 PM PDT 24
Peak memory 651420 kb
Host smart-1d09c42f-60ab-4544-970b-bc847bbbacbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1037373748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.1037373748 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.1563660888
Short name T980
Test name
Test status
Simulation time 49236604632 ps
CPU time 3343.73 seconds
Started Mar 19 01:07:59 PM PDT 24
Finished Mar 19 02:03:43 PM PDT 24
Peak memory 562648 kb
Host smart-086dcdb2-64d8-4ed1-b76d-4bab8b907daf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1563660888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.1563660888 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.2015682662
Short name T654
Test name
Test status
Simulation time 18722868 ps
CPU time 0.82 seconds
Started Mar 19 01:08:22 PM PDT 24
Finished Mar 19 01:08:24 PM PDT 24
Peak memory 205364 kb
Host smart-aba5147d-4b42-4f83-bf59-74db2e89cd10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015682662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.2015682662 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.789015071
Short name T386
Test name
Test status
Simulation time 4662006537 ps
CPU time 198.39 seconds
Started Mar 19 01:08:09 PM PDT 24
Finished Mar 19 01:11:28 PM PDT 24
Peak memory 240680 kb
Host smart-0c7ab42a-394b-4fbc-9553-799f4a7c774d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789015071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.789015071 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.3652326678
Short name T376
Test name
Test status
Simulation time 22982428945 ps
CPU time 717.66 seconds
Started Mar 19 01:08:09 PM PDT 24
Finished Mar 19 01:20:06 PM PDT 24
Peak memory 239584 kb
Host smart-16cf6fec-2bdd-4b34-8d2b-ba1eaca803a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652326678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3652326678 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.3973944883
Short name T394
Test name
Test status
Simulation time 15587395758 ps
CPU time 130.98 seconds
Started Mar 19 01:08:09 PM PDT 24
Finished Mar 19 01:10:21 PM PDT 24
Peak memory 233848 kb
Host smart-34f1bd12-8beb-4b22-a423-69a9835ffe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973944883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3973944883 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.3149155680
Short name T81
Test name
Test status
Simulation time 423854690 ps
CPU time 34.89 seconds
Started Mar 19 01:08:22 PM PDT 24
Finished Mar 19 01:08:58 PM PDT 24
Peak memory 238784 kb
Host smart-39687151-9c8d-4fc8-be35-7b1a1afac2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149155680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3149155680 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.1849624544
Short name T697
Test name
Test status
Simulation time 4354593374 ps
CPU time 5.05 seconds
Started Mar 19 01:08:20 PM PDT 24
Finished Mar 19 01:08:26 PM PDT 24
Peak memory 207620 kb
Host smart-a07ac8a8-b23f-42e7-9de9-5fa44b8f9e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849624544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.1849624544 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.467125817
Short name T794
Test name
Test status
Simulation time 134566988 ps
CPU time 1.31 seconds
Started Mar 19 01:08:18 PM PDT 24
Finished Mar 19 01:08:19 PM PDT 24
Peak memory 215800 kb
Host smart-f848db31-8d44-4d14-8ee1-14b0244b2e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467125817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.467125817 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.2802921479
Short name T401
Test name
Test status
Simulation time 15647548613 ps
CPU time 203.98 seconds
Started Mar 19 01:08:07 PM PDT 24
Finished Mar 19 01:11:31 PM PDT 24
Peak memory 238104 kb
Host smart-7a7012f5-28ac-45da-9ad5-408f96b4ff95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802921479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.2802921479 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.1529797275
Short name T135
Test name
Test status
Simulation time 24767671902 ps
CPU time 130.93 seconds
Started Mar 19 01:08:09 PM PDT 24
Finished Mar 19 01:10:20 PM PDT 24
Peak memory 229880 kb
Host smart-262ae0bb-5b5f-43ae-8239-1ebd8a92ae84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529797275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1529797275 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.1855226273
Short name T253
Test name
Test status
Simulation time 4478191254 ps
CPU time 45.61 seconds
Started Mar 19 01:08:08 PM PDT 24
Finished Mar 19 01:08:54 PM PDT 24
Peak memory 217088 kb
Host smart-0a230789-4c31-4a38-80a3-b338952e169c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855226273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.1855226273 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.3078012885
Short name T53
Test name
Test status
Simulation time 53359107734 ps
CPU time 1192.17 seconds
Started Mar 19 01:08:18 PM PDT 24
Finished Mar 19 01:28:10 PM PDT 24
Peak memory 360088 kb
Host smart-fe7ce67a-f349-4f7e-a244-e479aa61a2b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3078012885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3078012885 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.4135478966
Short name T245
Test name
Test status
Simulation time 425605415 ps
CPU time 4.55 seconds
Started Mar 19 01:08:09 PM PDT 24
Finished Mar 19 01:08:14 PM PDT 24
Peak memory 215976 kb
Host smart-4b72ae9e-342f-462c-9f52-5381bb502137
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135478966 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.4135478966 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.1050953024
Short name T1009
Test name
Test status
Simulation time 683151869 ps
CPU time 4.5 seconds
Started Mar 19 01:08:09 PM PDT 24
Finished Mar 19 01:08:14 PM PDT 24
Peak memory 208984 kb
Host smart-3ee8c95a-8820-47a7-a2dd-2ebdfc3fb12a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050953024 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.1050953024 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.3605681144
Short name T198
Test name
Test status
Simulation time 65362768232 ps
CPU time 1766.26 seconds
Started Mar 19 01:08:08 PM PDT 24
Finished Mar 19 01:37:35 PM PDT 24
Peak memory 391416 kb
Host smart-3ac61900-8313-47f8-bb49-df63d5ce8062
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3605681144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.3605681144 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.3454965905
Short name T987
Test name
Test status
Simulation time 40793451339 ps
CPU time 1500.33 seconds
Started Mar 19 01:08:08 PM PDT 24
Finished Mar 19 01:33:09 PM PDT 24
Peak memory 378904 kb
Host smart-ccfc073f-786d-4082-a16d-8fa91302b6a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3454965905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.3454965905 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.219115121
Short name T900
Test name
Test status
Simulation time 54223815732 ps
CPU time 1146.99 seconds
Started Mar 19 01:08:08 PM PDT 24
Finished Mar 19 01:27:16 PM PDT 24
Peak memory 332808 kb
Host smart-3e4a4201-ca9b-4147-aa2e-05331bf0756f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=219115121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.219115121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.965148434
Short name T668
Test name
Test status
Simulation time 41770277521 ps
CPU time 932.9 seconds
Started Mar 19 01:08:09 PM PDT 24
Finished Mar 19 01:23:42 PM PDT 24
Peak memory 292580 kb
Host smart-759367c0-6a58-4739-852a-7462797afdaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=965148434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.965148434 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.2385013525
Short name T632
Test name
Test status
Simulation time 1176105180634 ps
CPU time 5194.81 seconds
Started Mar 19 01:08:14 PM PDT 24
Finished Mar 19 02:34:49 PM PDT 24
Peak memory 659436 kb
Host smart-84375381-b154-4d7b-b26e-56c27e9b2b52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2385013525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.2385013525 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.474824811
Short name T583
Test name
Test status
Simulation time 206541423095 ps
CPU time 4051.03 seconds
Started Mar 19 01:08:10 PM PDT 24
Finished Mar 19 02:15:42 PM PDT 24
Peak memory 569028 kb
Host smart-ff4864cc-aa7a-464f-9b79-73aa5112bf74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=474824811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.474824811 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/36.kmac_alert_test.2235381070
Short name T412
Test name
Test status
Simulation time 28106010 ps
CPU time 0.76 seconds
Started Mar 19 01:08:33 PM PDT 24
Finished Mar 19 01:08:33 PM PDT 24
Peak memory 205392 kb
Host smart-02b78d9e-a559-41b8-90cf-397ef7e082ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235381070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.2235381070 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.1168194980
Short name T781
Test name
Test status
Simulation time 4034464911 ps
CPU time 95.96 seconds
Started Mar 19 01:08:32 PM PDT 24
Finished Mar 19 01:10:08 PM PDT 24
Peak memory 229572 kb
Host smart-aea7a3e8-8393-45a8-9b27-f69a52ac8c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168194980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.1168194980 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.641416923
Short name T1002
Test name
Test status
Simulation time 6168657772 ps
CPU time 175.89 seconds
Started Mar 19 01:08:20 PM PDT 24
Finished Mar 19 01:11:17 PM PDT 24
Peak memory 224424 kb
Host smart-bfc4555e-60aa-4839-8166-b6d5195b8ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641416923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.641416923 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_error.2670892790
Short name T704
Test name
Test status
Simulation time 572663595 ps
CPU time 11.05 seconds
Started Mar 19 01:08:32 PM PDT 24
Finished Mar 19 01:08:43 PM PDT 24
Peak memory 222292 kb
Host smart-81502863-9af2-4aa5-b09e-2ac0cdce2d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670892790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.2670892790 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.2304464571
Short name T977
Test name
Test status
Simulation time 740098844 ps
CPU time 4.23 seconds
Started Mar 19 01:08:31 PM PDT 24
Finished Mar 19 01:08:36 PM PDT 24
Peak memory 207316 kb
Host smart-e135f5f5-7b16-450c-9cc2-7849e6761d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304464571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.2304464571 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.3994649600
Short name T964
Test name
Test status
Simulation time 36452360 ps
CPU time 1.32 seconds
Started Mar 19 01:08:33 PM PDT 24
Finished Mar 19 01:08:34 PM PDT 24
Peak memory 215828 kb
Host smart-587cf1e0-5726-41e0-9ac2-95554a43e205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994649600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3994649600 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.649902912
Short name T1064
Test name
Test status
Simulation time 113681030233 ps
CPU time 2287.64 seconds
Started Mar 19 01:08:21 PM PDT 24
Finished Mar 19 01:46:30 PM PDT 24
Peak memory 461244 kb
Host smart-c6c61f1c-84a8-4eb9-9453-da3038ed9423
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649902912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_an
d_output.649902912 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.4083684722
Short name T378
Test name
Test status
Simulation time 16451303388 ps
CPU time 215.31 seconds
Started Mar 19 01:08:19 PM PDT 24
Finished Mar 19 01:11:55 PM PDT 24
Peak memory 238136 kb
Host smart-0ed953a7-9bf4-434d-adb5-f15b0d9841e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083684722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.4083684722 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.2343730643
Short name T307
Test name
Test status
Simulation time 1479898487 ps
CPU time 39.59 seconds
Started Mar 19 01:08:19 PM PDT 24
Finished Mar 19 01:08:59 PM PDT 24
Peak memory 219980 kb
Host smart-27ff617a-c00f-477a-9b33-a20e118c47d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343730643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.2343730643 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.639962054
Short name T426
Test name
Test status
Simulation time 48649210143 ps
CPU time 922.93 seconds
Started Mar 19 01:08:33 PM PDT 24
Finished Mar 19 01:23:56 PM PDT 24
Peak memory 328544 kb
Host smart-91076de4-bd70-4cb2-850f-2a2c4c794ea3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=639962054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.639962054 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_stress_all_with_rand_reset.2061698887
Short name T52
Test name
Test status
Simulation time 188330230610 ps
CPU time 2117.05 seconds
Started Mar 19 01:08:32 PM PDT 24
Finished Mar 19 01:43:49 PM PDT 24
Peak memory 417044 kb
Host smart-6638cb50-8516-40ba-8355-4f50f31b1cfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2061698887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all_with_rand_reset.2061698887 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.2801713112
Short name T67
Test name
Test status
Simulation time 79295167 ps
CPU time 4.03 seconds
Started Mar 19 01:08:33 PM PDT 24
Finished Mar 19 01:08:37 PM PDT 24
Peak memory 215944 kb
Host smart-6c0f12c8-6047-4c7e-9e62-4a7113a96964
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801713112 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.2801713112 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.830772542
Short name T984
Test name
Test status
Simulation time 249805610 ps
CPU time 5.14 seconds
Started Mar 19 01:08:32 PM PDT 24
Finished Mar 19 01:08:37 PM PDT 24
Peak memory 215980 kb
Host smart-be1fd2c2-4be2-463d-8698-7ba313a18bd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830772542 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.kmac_test_vectors_kmac_xof.830772542 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.1749924549
Short name T705
Test name
Test status
Simulation time 38433339545 ps
CPU time 1620.18 seconds
Started Mar 19 01:08:17 PM PDT 24
Finished Mar 19 01:35:17 PM PDT 24
Peak memory 392760 kb
Host smart-7078c8b7-63d7-48c0-9ba1-108bccdbc220
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1749924549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.1749924549 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.2210905394
Short name T456
Test name
Test status
Simulation time 245362652550 ps
CPU time 1735.88 seconds
Started Mar 19 01:08:18 PM PDT 24
Finished Mar 19 01:37:14 PM PDT 24
Peak memory 376008 kb
Host smart-159b08a0-092e-40ea-9aeb-b50b0373e39d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2210905394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.2210905394 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.2735045483
Short name T188
Test name
Test status
Simulation time 74089205831 ps
CPU time 1479.93 seconds
Started Mar 19 01:08:22 PM PDT 24
Finished Mar 19 01:33:03 PM PDT 24
Peak memory 338200 kb
Host smart-ecd52c6e-68e3-4550-bd94-0136ea2e704d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2735045483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.2735045483 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.1373057779
Short name T353
Test name
Test status
Simulation time 9591538278 ps
CPU time 814.07 seconds
Started Mar 19 01:08:18 PM PDT 24
Finished Mar 19 01:21:52 PM PDT 24
Peak memory 295164 kb
Host smart-03cfe817-a0a1-4471-82b5-236a1c5ad680
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1373057779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.1373057779 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.3861373547
Short name T445
Test name
Test status
Simulation time 51005088015 ps
CPU time 4245.4 seconds
Started Mar 19 01:08:19 PM PDT 24
Finished Mar 19 02:19:05 PM PDT 24
Peak memory 655096 kb
Host smart-7f6f46cc-826c-43af-a016-cc9fa8b52f6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3861373547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.3861373547 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.3998701677
Short name T39
Test name
Test status
Simulation time 217651906119 ps
CPU time 4096.27 seconds
Started Mar 19 01:08:17 PM PDT 24
Finished Mar 19 02:16:34 PM PDT 24
Peak memory 564704 kb
Host smart-fab151bb-3975-46c4-8dfe-2812ac6a480a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3998701677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.3998701677 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.140468025
Short name T581
Test name
Test status
Simulation time 39448239 ps
CPU time 0.76 seconds
Started Mar 19 01:08:49 PM PDT 24
Finished Mar 19 01:08:51 PM PDT 24
Peak memory 205348 kb
Host smart-cac154a3-1cfe-4277-8715-bb0409693927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140468025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.140468025 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.750127470
Short name T74
Test name
Test status
Simulation time 9587626122 ps
CPU time 169.33 seconds
Started Mar 19 01:08:49 PM PDT 24
Finished Mar 19 01:11:39 PM PDT 24
Peak memory 236132 kb
Host smart-77ed02ea-6c94-4fef-8c35-30a711be4bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750127470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.750127470 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.2272921701
Short name T793
Test name
Test status
Simulation time 60920887985 ps
CPU time 772.92 seconds
Started Mar 19 01:08:48 PM PDT 24
Finished Mar 19 01:21:42 PM PDT 24
Peak memory 231300 kb
Host smart-36b76cc9-0d0d-4b8e-9589-5c5ed324dff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272921701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.2272921701 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.1183728391
Short name T451
Test name
Test status
Simulation time 5058082248 ps
CPU time 105.76 seconds
Started Mar 19 01:08:49 PM PDT 24
Finished Mar 19 01:10:36 PM PDT 24
Peak memory 228624 kb
Host smart-3b12087b-42d5-4727-9ad4-dcb9255e72ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183728391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.1183728391 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.2806719013
Short name T553
Test name
Test status
Simulation time 21118917819 ps
CPU time 112.71 seconds
Started Mar 19 01:08:49 PM PDT 24
Finished Mar 19 01:10:42 PM PDT 24
Peak memory 248640 kb
Host smart-02ba6242-5ece-4871-911a-d4b6dec24154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806719013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.2806719013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.4005066415
Short name T840
Test name
Test status
Simulation time 1219797833 ps
CPU time 6.62 seconds
Started Mar 19 01:08:48 PM PDT 24
Finished Mar 19 01:08:56 PM PDT 24
Peak memory 207564 kb
Host smart-6c84edbc-a98d-4636-8f46-4895958363ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005066415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.4005066415 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.888409532
Short name T4
Test name
Test status
Simulation time 560335226 ps
CPU time 1.29 seconds
Started Mar 19 01:08:49 PM PDT 24
Finished Mar 19 01:08:52 PM PDT 24
Peak memory 216092 kb
Host smart-36ccd747-5f8d-4bcd-bf4c-c99c1b6dbe57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888409532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.888409532 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.1056757290
Short name T566
Test name
Test status
Simulation time 46350459061 ps
CPU time 1057.91 seconds
Started Mar 19 01:08:31 PM PDT 24
Finished Mar 19 01:26:09 PM PDT 24
Peak memory 320776 kb
Host smart-5c6cd005-0789-4194-9b5a-c5d7c94c48dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056757290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.1056757290 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.4169264999
Short name T243
Test name
Test status
Simulation time 16716301331 ps
CPU time 55.17 seconds
Started Mar 19 01:08:33 PM PDT 24
Finished Mar 19 01:09:29 PM PDT 24
Peak memory 224104 kb
Host smart-153a6831-50df-4634-8fb1-e6529843095a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169264999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.4169264999 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.2938565793
Short name T1030
Test name
Test status
Simulation time 1312349108 ps
CPU time 7.65 seconds
Started Mar 19 01:08:33 PM PDT 24
Finished Mar 19 01:08:41 PM PDT 24
Peak memory 217248 kb
Host smart-699c54bc-5608-44b5-b007-42542698bb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938565793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.2938565793 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.3196793082
Short name T791
Test name
Test status
Simulation time 21167584939 ps
CPU time 1071.72 seconds
Started Mar 19 01:08:48 PM PDT 24
Finished Mar 19 01:26:41 PM PDT 24
Peak memory 370000 kb
Host smart-ec4c536e-c69e-4b5d-b53e-a0ee3a6bbf58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3196793082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.3196793082 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.1335746636
Short name T375
Test name
Test status
Simulation time 423400700 ps
CPU time 5 seconds
Started Mar 19 01:08:48 PM PDT 24
Finished Mar 19 01:08:54 PM PDT 24
Peak memory 215936 kb
Host smart-1f467501-ef93-447e-b078-97f5a0f80945
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335746636 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.kmac_test_vectors_kmac.1335746636 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.1292928997
Short name T128
Test name
Test status
Simulation time 533873326 ps
CPU time 4.92 seconds
Started Mar 19 01:08:49 PM PDT 24
Finished Mar 19 01:08:54 PM PDT 24
Peak memory 216004 kb
Host smart-85470209-cb5e-4bf9-9e90-a1ab0039c68e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292928997 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.1292928997 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.2994643797
Short name T1041
Test name
Test status
Simulation time 298533522949 ps
CPU time 1847.82 seconds
Started Mar 19 01:08:48 PM PDT 24
Finished Mar 19 01:39:37 PM PDT 24
Peak memory 397856 kb
Host smart-2c7612cc-fc9b-477b-bcc2-810c91a1a51f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2994643797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.2994643797 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.3538661414
Short name T69
Test name
Test status
Simulation time 17488898179 ps
CPU time 1500.63 seconds
Started Mar 19 01:08:48 PM PDT 24
Finished Mar 19 01:33:50 PM PDT 24
Peak memory 369508 kb
Host smart-d7d243b5-cbfe-4b80-91df-234e9c1055b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3538661414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.3538661414 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.3184601142
Short name T612
Test name
Test status
Simulation time 14086296614 ps
CPU time 1098.73 seconds
Started Mar 19 01:08:49 PM PDT 24
Finished Mar 19 01:27:09 PM PDT 24
Peak memory 332252 kb
Host smart-4c276a7d-13ab-41a7-b384-e5f9dc48ddc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3184601142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.3184601142 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.4191835770
Short name T889
Test name
Test status
Simulation time 9996750448 ps
CPU time 786.94 seconds
Started Mar 19 01:08:48 PM PDT 24
Finished Mar 19 01:21:55 PM PDT 24
Peak memory 297064 kb
Host smart-97089fe3-37cd-41ed-9571-f7ac62bf6d2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4191835770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.4191835770 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.3102589667
Short name T766
Test name
Test status
Simulation time 104210516015 ps
CPU time 3970.2 seconds
Started Mar 19 01:08:50 PM PDT 24
Finished Mar 19 02:15:02 PM PDT 24
Peak memory 656124 kb
Host smart-e9533a09-c886-49ad-b1bc-f59d0427df61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3102589667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.3102589667 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.10104833
Short name T688
Test name
Test status
Simulation time 994526431699 ps
CPU time 4478.3 seconds
Started Mar 19 01:08:50 PM PDT 24
Finished Mar 19 02:23:30 PM PDT 24
Peak memory 569800 kb
Host smart-45515ba1-855b-4b0c-990e-241c707b2a1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=10104833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.10104833 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.2167486101
Short name T240
Test name
Test status
Simulation time 144959712 ps
CPU time 0.72 seconds
Started Mar 19 01:08:59 PM PDT 24
Finished Mar 19 01:09:00 PM PDT 24
Peak memory 205332 kb
Host smart-76d566f9-cb53-44a1-aa45-5e6473aa338b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167486101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.2167486101 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.1665081675
Short name T540
Test name
Test status
Simulation time 5742461955 ps
CPU time 258.78 seconds
Started Mar 19 01:08:58 PM PDT 24
Finished Mar 19 01:13:18 PM PDT 24
Peak memory 248144 kb
Host smart-3884b058-fe61-4e73-b834-b2d91320d1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665081675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1665081675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.1232250570
Short name T761
Test name
Test status
Simulation time 86014608549 ps
CPU time 735.86 seconds
Started Mar 19 01:09:00 PM PDT 24
Finished Mar 19 01:21:16 PM PDT 24
Peak memory 231988 kb
Host smart-485d8dbc-2542-4760-b6a0-e985dd4033a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232250570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.1232250570 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.1408984572
Short name T31
Test name
Test status
Simulation time 8923965034 ps
CPU time 222.4 seconds
Started Mar 19 01:08:59 PM PDT 24
Finished Mar 19 01:12:43 PM PDT 24
Peak memory 240400 kb
Host smart-764e1886-4dca-40d5-b3f0-22a5337c165a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408984572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1408984572 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.2014863879
Short name T627
Test name
Test status
Simulation time 57309110169 ps
CPU time 379.78 seconds
Started Mar 19 01:09:04 PM PDT 24
Finished Mar 19 01:15:24 PM PDT 24
Peak memory 256848 kb
Host smart-a2d5d2ec-3b65-42f0-8464-39c00579391e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014863879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.2014863879 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.1531625952
Short name T26
Test name
Test status
Simulation time 640696020 ps
CPU time 1.98 seconds
Started Mar 19 01:08:59 PM PDT 24
Finished Mar 19 01:09:01 PM PDT 24
Peak memory 207452 kb
Host smart-c942cc42-0a8b-4318-be2d-06af2e01a911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531625952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1531625952 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.2119111131
Short name T1021
Test name
Test status
Simulation time 69968721 ps
CPU time 1.52 seconds
Started Mar 19 01:09:02 PM PDT 24
Finished Mar 19 01:09:03 PM PDT 24
Peak memory 215860 kb
Host smart-65a103e8-0266-40a2-9e81-7410f52fe733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119111131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.2119111131 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.2150575380
Short name T974
Test name
Test status
Simulation time 102323654803 ps
CPU time 2179.67 seconds
Started Mar 19 01:08:59 PM PDT 24
Finished Mar 19 01:45:19 PM PDT 24
Peak memory 422296 kb
Host smart-c9949a04-67a5-43a6-a0bc-8f57e2f558ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150575380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.2150575380 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.1843230421
Short name T615
Test name
Test status
Simulation time 210266736 ps
CPU time 15.82 seconds
Started Mar 19 01:08:59 PM PDT 24
Finished Mar 19 01:09:16 PM PDT 24
Peak memory 218044 kb
Host smart-b1d0ed5d-e753-4286-aefa-55bb53b38d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843230421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.1843230421 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.3396110065
Short name T899
Test name
Test status
Simulation time 20535296103 ps
CPU time 43.42 seconds
Started Mar 19 01:08:51 PM PDT 24
Finished Mar 19 01:09:36 PM PDT 24
Peak memory 220660 kb
Host smart-fb82ce4d-cfef-46d2-bc1c-3c8384c3b394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396110065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.3396110065 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.3016967035
Short name T338
Test name
Test status
Simulation time 84722106230 ps
CPU time 1273.62 seconds
Started Mar 19 01:09:04 PM PDT 24
Finished Mar 19 01:30:18 PM PDT 24
Peak memory 416320 kb
Host smart-a0ad1e92-cf88-4c3d-baa8-d31af9d1e314
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3016967035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.3016967035 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.2257759661
Short name T357
Test name
Test status
Simulation time 284961267 ps
CPU time 4.65 seconds
Started Mar 19 01:09:03 PM PDT 24
Finished Mar 19 01:09:08 PM PDT 24
Peak memory 215932 kb
Host smart-f954784b-296b-4589-a45b-97ba4cb6177c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257759661 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.kmac_test_vectors_kmac.2257759661 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.251897441
Short name T536
Test name
Test status
Simulation time 628446315 ps
CPU time 4.07 seconds
Started Mar 19 01:09:02 PM PDT 24
Finished Mar 19 01:09:06 PM PDT 24
Peak memory 208956 kb
Host smart-3c584d5c-b728-45cf-b277-46ca8488d4d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251897441 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.kmac_test_vectors_kmac_xof.251897441 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.2677347943
Short name T1026
Test name
Test status
Simulation time 67793284541 ps
CPU time 1810.42 seconds
Started Mar 19 01:08:59 PM PDT 24
Finished Mar 19 01:39:10 PM PDT 24
Peak memory 392976 kb
Host smart-dddab058-d7ad-4edb-b450-4d9fff55f96a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2677347943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.2677347943 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.1448765342
Short name T440
Test name
Test status
Simulation time 71124948766 ps
CPU time 1509.84 seconds
Started Mar 19 01:09:00 PM PDT 24
Finished Mar 19 01:34:10 PM PDT 24
Peak memory 374280 kb
Host smart-663ed387-5385-4eaf-a4f7-b13ab6272d3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1448765342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.1448765342 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.400545639
Short name T586
Test name
Test status
Simulation time 47565403810 ps
CPU time 1357.45 seconds
Started Mar 19 01:08:59 PM PDT 24
Finished Mar 19 01:31:37 PM PDT 24
Peak memory 335268 kb
Host smart-f3be6a92-0b7b-4f9d-99c7-f9125303a451
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=400545639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.400545639 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.373478080
Short name T843
Test name
Test status
Simulation time 38595266211 ps
CPU time 829.18 seconds
Started Mar 19 01:08:58 PM PDT 24
Finished Mar 19 01:22:48 PM PDT 24
Peak memory 297124 kb
Host smart-bad62d59-0c22-4c47-a14e-b344195302ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=373478080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.373478080 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.3648813239
Short name T606
Test name
Test status
Simulation time 51665980363 ps
CPU time 4120.65 seconds
Started Mar 19 01:08:59 PM PDT 24
Finished Mar 19 02:17:41 PM PDT 24
Peak memory 644928 kb
Host smart-cb53dbe5-3e78-48f7-ba59-f6c32993e6bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3648813239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.3648813239 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.2771341795
Short name T510
Test name
Test status
Simulation time 154418657219 ps
CPU time 3496.32 seconds
Started Mar 19 01:09:00 PM PDT 24
Finished Mar 19 02:07:17 PM PDT 24
Peak memory 560804 kb
Host smart-d4c68e5f-3bc7-462e-8653-152d3ff6aeef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2771341795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.2771341795 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.2195520593
Short name T1011
Test name
Test status
Simulation time 17930921 ps
CPU time 0.81 seconds
Started Mar 19 01:09:26 PM PDT 24
Finished Mar 19 01:09:27 PM PDT 24
Peak memory 205300 kb
Host smart-dba899f9-2528-45e8-ab3e-cfe9745623b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195520593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.2195520593 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.3097264980
Short name T517
Test name
Test status
Simulation time 32030142214 ps
CPU time 293.34 seconds
Started Mar 19 01:09:14 PM PDT 24
Finished Mar 19 01:14:07 PM PDT 24
Peak memory 245796 kb
Host smart-03a9c1bf-ae7c-4530-a3b7-34ed8ac57e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097264980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.3097264980 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.737734902
Short name T1034
Test name
Test status
Simulation time 45687478104 ps
CPU time 277.51 seconds
Started Mar 19 01:09:13 PM PDT 24
Finished Mar 19 01:13:50 PM PDT 24
Peak memory 226544 kb
Host smart-8435ab60-cfc7-4c08-bc27-97c6de5f8c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737734902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.737734902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.3085040827
Short name T110
Test name
Test status
Simulation time 26341365841 ps
CPU time 200.57 seconds
Started Mar 19 01:09:12 PM PDT 24
Finished Mar 19 01:12:32 PM PDT 24
Peak memory 239292 kb
Host smart-122013c9-2a48-4541-bc87-38b5910a75cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085040827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.3085040827 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.187587930
Short name T422
Test name
Test status
Simulation time 13332052279 ps
CPU time 369.62 seconds
Started Mar 19 01:09:13 PM PDT 24
Finished Mar 19 01:15:23 PM PDT 24
Peak memory 256628 kb
Host smart-de596570-2499-48c7-8a20-9beac8446c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187587930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.187587930 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.3348079072
Short name T369
Test name
Test status
Simulation time 355071281 ps
CPU time 2.34 seconds
Started Mar 19 01:09:26 PM PDT 24
Finished Mar 19 01:09:28 PM PDT 24
Peak memory 206912 kb
Host smart-f30f83fe-903a-41d4-9e32-689878c8eb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348079072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3348079072 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.1153716635
Short name T373
Test name
Test status
Simulation time 40707258 ps
CPU time 1.28 seconds
Started Mar 19 01:09:22 PM PDT 24
Finished Mar 19 01:09:23 PM PDT 24
Peak memory 215852 kb
Host smart-046fd000-87be-4cf2-83ee-a7fefc0c4813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153716635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1153716635 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.2458052501
Short name T391
Test name
Test status
Simulation time 230196549511 ps
CPU time 2554.39 seconds
Started Mar 19 01:09:12 PM PDT 24
Finished Mar 19 01:51:47 PM PDT 24
Peak memory 459516 kb
Host smart-bb2cbb23-77ab-4636-9edc-aef04d8d372d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458052501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.2458052501 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.3414338468
Short name T531
Test name
Test status
Simulation time 134027697353 ps
CPU time 467.84 seconds
Started Mar 19 01:09:14 PM PDT 24
Finished Mar 19 01:17:03 PM PDT 24
Peak memory 248936 kb
Host smart-9aeb9638-33c6-48f4-a487-c0b8dd1d0fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414338468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.3414338468 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.1296269597
Short name T491
Test name
Test status
Simulation time 2635263258 ps
CPU time 28.17 seconds
Started Mar 19 01:09:14 PM PDT 24
Finished Mar 19 01:09:42 PM PDT 24
Peak memory 219588 kb
Host smart-c9f07b31-aff1-4f27-a0cd-50ddc8ab3007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296269597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1296269597 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.3317688946
Short name T327
Test name
Test status
Simulation time 36146047751 ps
CPU time 267.14 seconds
Started Mar 19 01:09:21 PM PDT 24
Finished Mar 19 01:13:48 PM PDT 24
Peak memory 248872 kb
Host smart-5c092961-aab7-4c35-b95f-bce3ab545623
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3317688946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.3317688946 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.4075863532
Short name T301
Test name
Test status
Simulation time 251562391 ps
CPU time 4.08 seconds
Started Mar 19 01:09:12 PM PDT 24
Finished Mar 19 01:09:16 PM PDT 24
Peak memory 215984 kb
Host smart-0139b2a1-5439-4f57-b61d-abee950a4fb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075863532 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.kmac_test_vectors_kmac.4075863532 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.300318267
Short name T752
Test name
Test status
Simulation time 233546243 ps
CPU time 4.8 seconds
Started Mar 19 01:09:11 PM PDT 24
Finished Mar 19 01:09:16 PM PDT 24
Peak memory 215976 kb
Host smart-2b460ed8-fd21-483a-87e1-c613b613a79e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300318267 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.kmac_test_vectors_kmac_xof.300318267 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.610012170
Short name T497
Test name
Test status
Simulation time 44085423614 ps
CPU time 1527.46 seconds
Started Mar 19 01:09:13 PM PDT 24
Finished Mar 19 01:34:42 PM PDT 24
Peak memory 377984 kb
Host smart-e79f9de6-4cb0-4800-9966-981640be741d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=610012170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.610012170 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.1206299688
Short name T1017
Test name
Test status
Simulation time 1198634064890 ps
CPU time 2133.88 seconds
Started Mar 19 01:09:14 PM PDT 24
Finished Mar 19 01:44:48 PM PDT 24
Peak memory 366912 kb
Host smart-fa7c30dc-c3fa-494e-ba7d-5187f985bea4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1206299688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.1206299688 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.3751324900
Short name T235
Test name
Test status
Simulation time 293781389244 ps
CPU time 1438.43 seconds
Started Mar 19 01:09:14 PM PDT 24
Finished Mar 19 01:33:13 PM PDT 24
Peak memory 336448 kb
Host smart-299c9a4e-1171-4ed7-ad9a-789f0bf2a76c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3751324900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.3751324900 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.2390109729
Short name T288
Test name
Test status
Simulation time 251802911452 ps
CPU time 939.4 seconds
Started Mar 19 01:09:14 PM PDT 24
Finished Mar 19 01:24:54 PM PDT 24
Peak memory 295976 kb
Host smart-feadac29-9ab5-43f0-beba-7b47b24e3633
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2390109729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.2390109729 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.2593966987
Short name T424
Test name
Test status
Simulation time 920436719135 ps
CPU time 4919.73 seconds
Started Mar 19 01:09:11 PM PDT 24
Finished Mar 19 02:31:11 PM PDT 24
Peak memory 641700 kb
Host smart-293c4260-2c2a-4b4a-84ba-1ee4d360c31b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2593966987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.2593966987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.3764965623
Short name T447
Test name
Test status
Simulation time 125575173194 ps
CPU time 3373.22 seconds
Started Mar 19 01:09:14 PM PDT 24
Finished Mar 19 02:05:28 PM PDT 24
Peak memory 550604 kb
Host smart-44237a5e-846e-4f5c-8200-276d6e8bf1ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3764965623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.3764965623 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.415113317
Short name T237
Test name
Test status
Simulation time 15480845 ps
CPU time 0.8 seconds
Started Mar 19 01:03:59 PM PDT 24
Finished Mar 19 01:04:00 PM PDT 24
Peak memory 205396 kb
Host smart-40b7180b-caf4-43e2-8eb7-ab70c6535df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415113317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.415113317 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.751411961
Short name T150
Test name
Test status
Simulation time 20812388696 ps
CPU time 88.18 seconds
Started Mar 19 01:03:56 PM PDT 24
Finished Mar 19 01:05:24 PM PDT 24
Peak memory 228376 kb
Host smart-8de2f80b-4542-4ae9-9e67-d55c93e55cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751411961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.751411961 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.4221282616
Short name T911
Test name
Test status
Simulation time 11108765129 ps
CPU time 193.95 seconds
Started Mar 19 01:03:58 PM PDT 24
Finished Mar 19 01:07:12 PM PDT 24
Peak memory 236528 kb
Host smart-2fb43310-943a-44d7-83a7-1512a6d1de2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221282616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.4221282616 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.395888814
Short name T430
Test name
Test status
Simulation time 101593804010 ps
CPU time 394.66 seconds
Started Mar 19 01:03:46 PM PDT 24
Finished Mar 19 01:10:22 PM PDT 24
Peak memory 228448 kb
Host smart-a5b919d0-50cc-46b4-8678-42f9f60355b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395888814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.395888814 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.1933230544
Short name T303
Test name
Test status
Simulation time 281383395 ps
CPU time 19.84 seconds
Started Mar 19 01:03:55 PM PDT 24
Finished Mar 19 01:04:16 PM PDT 24
Peak memory 224028 kb
Host smart-191200f2-ad23-4ae7-ab5f-54ac290f7c0b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1933230544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.1933230544 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.447800813
Short name T828
Test name
Test status
Simulation time 70337138 ps
CPU time 1 seconds
Started Mar 19 01:03:58 PM PDT 24
Finished Mar 19 01:03:59 PM PDT 24
Peak memory 205392 kb
Host smart-087d822a-9c2e-491a-a602-d076832daca8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=447800813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.447800813 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.4006474132
Short name T1065
Test name
Test status
Simulation time 30160156935 ps
CPU time 47.4 seconds
Started Mar 19 01:03:59 PM PDT 24
Finished Mar 19 01:04:46 PM PDT 24
Peak memory 215952 kb
Host smart-9e4f1e9f-b1f3-4b08-a0ab-2c4be5d2fa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006474132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.4006474132 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.435372741
Short name T576
Test name
Test status
Simulation time 22865859842 ps
CPU time 188.18 seconds
Started Mar 19 01:03:54 PM PDT 24
Finished Mar 19 01:07:04 PM PDT 24
Peak memory 237432 kb
Host smart-eb85f11d-ef9a-4677-a01e-69ff051d7cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435372741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.435372741 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.3507085836
Short name T371
Test name
Test status
Simulation time 2660854560 ps
CPU time 184.77 seconds
Started Mar 19 01:03:57 PM PDT 24
Finished Mar 19 01:07:02 PM PDT 24
Peak memory 256072 kb
Host smart-3ab0b5c8-c690-48bf-8dcf-13fd67786987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507085836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.3507085836 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.3508278899
Short name T616
Test name
Test status
Simulation time 2475471776 ps
CPU time 2.85 seconds
Started Mar 19 01:03:57 PM PDT 24
Finished Mar 19 01:04:01 PM PDT 24
Peak memory 207548 kb
Host smart-d3ffc5f9-cb5b-4b1a-813a-011fb7257a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508278899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.3508278899 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.4122625127
Short name T706
Test name
Test status
Simulation time 42629329 ps
CPU time 1.15 seconds
Started Mar 19 01:03:57 PM PDT 24
Finished Mar 19 01:03:58 PM PDT 24
Peak memory 215848 kb
Host smart-d9e0e57d-9edf-4649-91a5-63cb7b68e585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122625127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.4122625127 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.431398465
Short name T289
Test name
Test status
Simulation time 313737892283 ps
CPU time 2342.73 seconds
Started Mar 19 01:03:47 PM PDT 24
Finished Mar 19 01:42:52 PM PDT 24
Peak memory 436148 kb
Host smart-b96c66a8-8dbb-42ca-a2e9-db3da040497c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431398465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and
_output.431398465 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.861826098
Short name T895
Test name
Test status
Simulation time 53184075660 ps
CPU time 321.6 seconds
Started Mar 19 01:03:56 PM PDT 24
Finished Mar 19 01:09:18 PM PDT 24
Peak memory 249084 kb
Host smart-b3c7a7a4-fcf8-42d0-a99f-8cef6c4a5e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861826098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.861826098 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.2016038696
Short name T11
Test name
Test status
Simulation time 2543267326 ps
CPU time 33.63 seconds
Started Mar 19 01:03:55 PM PDT 24
Finished Mar 19 01:04:30 PM PDT 24
Peak memory 243356 kb
Host smart-0a0476dc-f1f8-4419-a822-48829c232c16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016038696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2016038696 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.2702838538
Short name T227
Test name
Test status
Simulation time 20943382338 ps
CPU time 296.71 seconds
Started Mar 19 01:04:01 PM PDT 24
Finished Mar 19 01:08:58 PM PDT 24
Peak memory 243668 kb
Host smart-90e922d2-dd7e-4ee1-b16f-47bbf5dfef4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702838538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.2702838538 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.1916158130
Short name T795
Test name
Test status
Simulation time 1765039288 ps
CPU time 15.97 seconds
Started Mar 19 01:03:50 PM PDT 24
Finished Mar 19 01:04:08 PM PDT 24
Peak memory 223992 kb
Host smart-3b74c339-adce-4b02-9a64-2344324e1701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916158130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.1916158130 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.4269015619
Short name T569
Test name
Test status
Simulation time 25728134719 ps
CPU time 532.83 seconds
Started Mar 19 01:03:57 PM PDT 24
Finished Mar 19 01:12:51 PM PDT 24
Peak memory 300396 kb
Host smart-d43c8aa6-dd9f-4b6a-9757-8f7f6367ed07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4269015619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.4269015619 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_stress_all_with_rand_reset.3555173451
Short name T51
Test name
Test status
Simulation time 42148977997 ps
CPU time 555.33 seconds
Started Mar 19 01:03:59 PM PDT 24
Finished Mar 19 01:13:15 PM PDT 24
Peak memory 286916 kb
Host smart-81a0b627-c033-458c-809e-8c3916cac2ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3555173451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_with_rand_reset.3555173451 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.3613729078
Short name T1003
Test name
Test status
Simulation time 141011575 ps
CPU time 4.32 seconds
Started Mar 19 01:03:57 PM PDT 24
Finished Mar 19 01:04:02 PM PDT 24
Peak memory 216008 kb
Host smart-63637a27-ea53-4dbb-9893-aefee72a0832
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613729078 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.3613729078 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.1840018582
Short name T855
Test name
Test status
Simulation time 346031988 ps
CPU time 4.41 seconds
Started Mar 19 01:03:56 PM PDT 24
Finished Mar 19 01:04:01 PM PDT 24
Peak memory 215968 kb
Host smart-03d239b6-987a-42b1-923f-c6154d875a4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840018582 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.1840018582 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.2522362241
Short name T733
Test name
Test status
Simulation time 346512204414 ps
CPU time 1814.64 seconds
Started Mar 19 01:03:52 PM PDT 24
Finished Mar 19 01:34:08 PM PDT 24
Peak memory 387928 kb
Host smart-66641383-6114-4fbf-ba8f-404686abd00c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2522362241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2522362241 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.692097135
Short name T1005
Test name
Test status
Simulation time 331739449042 ps
CPU time 1875.84 seconds
Started Mar 19 01:04:00 PM PDT 24
Finished Mar 19 01:35:17 PM PDT 24
Peak memory 376192 kb
Host smart-e456e9da-c53e-4c54-ba50-a6d12b3f7b8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=692097135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.692097135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.3865070982
Short name T748
Test name
Test status
Simulation time 195553461077 ps
CPU time 1289.28 seconds
Started Mar 19 01:03:59 PM PDT 24
Finished Mar 19 01:25:28 PM PDT 24
Peak memory 335108 kb
Host smart-713d0320-2b01-429a-9d46-bc67b8c0fd41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3865070982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.3865070982 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.645027067
Short name T1081
Test name
Test status
Simulation time 219018653931 ps
CPU time 942.45 seconds
Started Mar 19 01:03:57 PM PDT 24
Finished Mar 19 01:19:40 PM PDT 24
Peak memory 301472 kb
Host smart-3874c185-8421-4e17-92ba-53f1b84a41b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=645027067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.645027067 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.3112629902
Short name T931
Test name
Test status
Simulation time 515046013346 ps
CPU time 4303.51 seconds
Started Mar 19 01:03:59 PM PDT 24
Finished Mar 19 02:15:43 PM PDT 24
Peak memory 664392 kb
Host smart-58f65126-5d40-459f-a3ca-462fb2f2ebb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3112629902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.3112629902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.2303122236
Short name T779
Test name
Test status
Simulation time 150478972877 ps
CPU time 3998.59 seconds
Started Mar 19 01:03:57 PM PDT 24
Finished Mar 19 02:10:36 PM PDT 24
Peak memory 565928 kb
Host smart-ae10b9dc-f9fd-49d3-8623-826b753f00f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2303122236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2303122236 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.1809705172
Short name T415
Test name
Test status
Simulation time 24348498 ps
CPU time 0.76 seconds
Started Mar 19 01:09:32 PM PDT 24
Finished Mar 19 01:09:33 PM PDT 24
Peak memory 205332 kb
Host smart-01e6f888-d802-4838-8076-9b4061e01680
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809705172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.1809705172 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.3412132161
Short name T408
Test name
Test status
Simulation time 7829245175 ps
CPU time 221.9 seconds
Started Mar 19 01:09:33 PM PDT 24
Finished Mar 19 01:13:15 PM PDT 24
Peak memory 243608 kb
Host smart-9ed9e2f3-d560-4d96-99fc-81c41758fad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412132161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.3412132161 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.654992160
Short name T247
Test name
Test status
Simulation time 7062121172 ps
CPU time 609.18 seconds
Started Mar 19 01:09:24 PM PDT 24
Finished Mar 19 01:19:34 PM PDT 24
Peak memory 230928 kb
Host smart-a49d1ed6-b680-419d-8034-b56e9220514d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654992160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.654992160 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.2834543902
Short name T571
Test name
Test status
Simulation time 57942059438 ps
CPU time 249.24 seconds
Started Mar 19 01:09:33 PM PDT 24
Finished Mar 19 01:13:42 PM PDT 24
Peak memory 241296 kb
Host smart-2d3506bc-f239-4f9e-bbf8-d9ae786eadc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834543902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.2834543902 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.1010282339
Short name T865
Test name
Test status
Simulation time 4171803061 ps
CPU time 112.51 seconds
Started Mar 19 01:09:34 PM PDT 24
Finished Mar 19 01:11:26 PM PDT 24
Peak memory 238044 kb
Host smart-9b6dc53e-a6a0-4251-b357-572848684358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010282339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1010282339 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.4070581616
Short name T1066
Test name
Test status
Simulation time 3784342117 ps
CPU time 5.15 seconds
Started Mar 19 01:09:32 PM PDT 24
Finished Mar 19 01:09:38 PM PDT 24
Peak memory 207512 kb
Host smart-34d0fbda-101e-4f17-b26f-d93adb3719a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070581616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.4070581616 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.159319337
Short name T695
Test name
Test status
Simulation time 9068345352 ps
CPU time 70.05 seconds
Started Mar 19 01:09:22 PM PDT 24
Finished Mar 19 01:10:33 PM PDT 24
Peak memory 224116 kb
Host smart-444c11e9-ca9e-4343-b1a9-18818e3761bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159319337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_an
d_output.159319337 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.3549219522
Short name T287
Test name
Test status
Simulation time 11583554936 ps
CPU time 217.1 seconds
Started Mar 19 01:09:26 PM PDT 24
Finished Mar 19 01:13:03 PM PDT 24
Peak memory 240756 kb
Host smart-1bbd049d-f543-4587-bb6f-84b9eecee3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549219522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3549219522 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.3391980449
Short name T798
Test name
Test status
Simulation time 1956376347 ps
CPU time 39.88 seconds
Started Mar 19 01:09:20 PM PDT 24
Finished Mar 19 01:10:00 PM PDT 24
Peak memory 222016 kb
Host smart-f42d036a-f3b4-477b-ab01-c1d1949c9bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391980449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.3391980449 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.1109671294
Short name T800
Test name
Test status
Simulation time 61288834166 ps
CPU time 1198.8 seconds
Started Mar 19 01:09:32 PM PDT 24
Finished Mar 19 01:29:31 PM PDT 24
Peak memory 339280 kb
Host smart-6d7bfdec-e4ed-4c53-83e4-57c3bd61e5f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1109671294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.1109671294 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.2187828027
Short name T1042
Test name
Test status
Simulation time 1334705183 ps
CPU time 5.09 seconds
Started Mar 19 01:09:21 PM PDT 24
Finished Mar 19 01:09:26 PM PDT 24
Peak memory 209356 kb
Host smart-e54c86f5-82a0-4711-9a9a-03f316762dc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187828027 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.kmac_test_vectors_kmac.2187828027 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.2881487093
Short name T308
Test name
Test status
Simulation time 140678766 ps
CPU time 4.13 seconds
Started Mar 19 01:09:22 PM PDT 24
Finished Mar 19 01:09:26 PM PDT 24
Peak memory 215944 kb
Host smart-9a1a184c-0f1f-41dc-9923-7ef7ca633c8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881487093 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.kmac_test_vectors_kmac_xof.2881487093 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.83329166
Short name T837
Test name
Test status
Simulation time 19396064004 ps
CPU time 1633.82 seconds
Started Mar 19 01:09:21 PM PDT 24
Finished Mar 19 01:36:35 PM PDT 24
Peak memory 399636 kb
Host smart-b97747bf-7709-44bd-900a-fef53122c0ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=83329166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.83329166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.4243238602
Short name T482
Test name
Test status
Simulation time 18888111677 ps
CPU time 1513.75 seconds
Started Mar 19 01:09:21 PM PDT 24
Finished Mar 19 01:34:35 PM PDT 24
Peak memory 389384 kb
Host smart-45faf006-d8bb-44cf-8db1-0be155798396
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4243238602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.4243238602 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.3579626246
Short name T582
Test name
Test status
Simulation time 95079439020 ps
CPU time 1105.97 seconds
Started Mar 19 01:09:20 PM PDT 24
Finished Mar 19 01:27:47 PM PDT 24
Peak memory 328568 kb
Host smart-3f36430e-1d15-4af2-bcce-2ee92ee97c27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3579626246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.3579626246 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.3717830236
Short name T441
Test name
Test status
Simulation time 49350965000 ps
CPU time 954.52 seconds
Started Mar 19 01:09:25 PM PDT 24
Finished Mar 19 01:25:19 PM PDT 24
Peak memory 293392 kb
Host smart-8abd5329-d516-4625-8cef-4d2a90c1690a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3717830236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.3717830236 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.971561563
Short name T452
Test name
Test status
Simulation time 652144834195 ps
CPU time 5082.34 seconds
Started Mar 19 01:09:20 PM PDT 24
Finished Mar 19 02:34:04 PM PDT 24
Peak memory 636072 kb
Host smart-a023b830-69bb-42e7-a118-8af4a64dcb9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=971561563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.971561563 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.3025910323
Short name T259
Test name
Test status
Simulation time 597025504565 ps
CPU time 4155.12 seconds
Started Mar 19 01:09:21 PM PDT 24
Finished Mar 19 02:18:37 PM PDT 24
Peak memory 549408 kb
Host smart-df9bf041-3e71-4507-a3e0-b9aa426a6ee7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3025910323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.3025910323 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.1756033776
Short name T936
Test name
Test status
Simulation time 16515909 ps
CPU time 0.79 seconds
Started Mar 19 01:09:44 PM PDT 24
Finished Mar 19 01:09:45 PM PDT 24
Peak memory 205308 kb
Host smart-627c9025-f32e-47af-a5b2-4459e1a50e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756033776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.1756033776 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.2250978698
Short name T1006
Test name
Test status
Simulation time 5800014971 ps
CPU time 110.13 seconds
Started Mar 19 01:09:44 PM PDT 24
Finished Mar 19 01:11:34 PM PDT 24
Peak memory 238728 kb
Host smart-a8d83a57-be3f-4799-bd20-a02f247573d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250978698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2250978698 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.916470681
Short name T515
Test name
Test status
Simulation time 75853293306 ps
CPU time 407.3 seconds
Started Mar 19 01:09:42 PM PDT 24
Finished Mar 19 01:16:29 PM PDT 24
Peak memory 229696 kb
Host smart-9f50a800-856b-4a82-9c0e-d925902de444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916470681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.916470681 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_error.3119100153
Short name T986
Test name
Test status
Simulation time 2229980200 ps
CPU time 41.22 seconds
Started Mar 19 01:09:41 PM PDT 24
Finished Mar 19 01:10:22 PM PDT 24
Peak memory 232348 kb
Host smart-ddeee352-41b8-4f15-93cd-e865ca7610d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119100153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.3119100153 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.814021013
Short name T532
Test name
Test status
Simulation time 961535545 ps
CPU time 2.15 seconds
Started Mar 19 01:09:46 PM PDT 24
Finished Mar 19 01:09:49 PM PDT 24
Peak memory 207268 kb
Host smart-3f97f1f7-28a5-4a10-8c71-8e275ae4aae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814021013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.814021013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.3721563672
Short name T416
Test name
Test status
Simulation time 231340753 ps
CPU time 1.38 seconds
Started Mar 19 01:09:43 PM PDT 24
Finished Mar 19 01:09:44 PM PDT 24
Peak memory 215772 kb
Host smart-1b5c1286-7c5c-4974-9b75-1bc75ab86964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721563672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.3721563672 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.2615202934
Short name T852
Test name
Test status
Simulation time 185725508014 ps
CPU time 1931.47 seconds
Started Mar 19 01:09:46 PM PDT 24
Finished Mar 19 01:41:58 PM PDT 24
Peak memory 391052 kb
Host smart-3a652f9c-0c6a-4033-abc7-d3631adc6e6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615202934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.2615202934 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.2866362371
Short name T251
Test name
Test status
Simulation time 13654792119 ps
CPU time 282.84 seconds
Started Mar 19 01:09:42 PM PDT 24
Finished Mar 19 01:14:25 PM PDT 24
Peak memory 243640 kb
Host smart-678398cd-0e17-4fb8-9b10-98c901bd140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866362371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.2866362371 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.4038221749
Short name T647
Test name
Test status
Simulation time 12715724852 ps
CPU time 59.43 seconds
Started Mar 19 01:09:44 PM PDT 24
Finished Mar 19 01:10:44 PM PDT 24
Peak memory 216412 kb
Host smart-c03b0ad9-118c-42cf-9f84-660caecde04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038221749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.4038221749 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.2480475927
Short name T568
Test name
Test status
Simulation time 27864874474 ps
CPU time 495.09 seconds
Started Mar 19 01:09:43 PM PDT 24
Finished Mar 19 01:17:59 PM PDT 24
Peak memory 295888 kb
Host smart-d258f36a-e4da-4507-a3e8-bfcd50bc3d96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2480475927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.2480475927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.447465141
Short name T222
Test name
Test status
Simulation time 257283136 ps
CPU time 3.87 seconds
Started Mar 19 01:09:44 PM PDT 24
Finished Mar 19 01:09:48 PM PDT 24
Peak memory 215864 kb
Host smart-61166310-dc44-42cd-86e5-4e1557eed8c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447465141 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.kmac_test_vectors_kmac.447465141 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.2281054991
Short name T780
Test name
Test status
Simulation time 268106934 ps
CPU time 4.13 seconds
Started Mar 19 01:09:42 PM PDT 24
Finished Mar 19 01:09:46 PM PDT 24
Peak memory 208916 kb
Host smart-30db6799-1415-47c4-a79c-af36107108c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281054991 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.2281054991 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.1289272667
Short name T213
Test name
Test status
Simulation time 67182871096 ps
CPU time 1854.76 seconds
Started Mar 19 01:09:42 PM PDT 24
Finished Mar 19 01:40:37 PM PDT 24
Peak memory 379008 kb
Host smart-c0280e09-9184-4456-976d-a83354687e19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1289272667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.1289272667 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.507731583
Short name T322
Test name
Test status
Simulation time 18579796769 ps
CPU time 1574.33 seconds
Started Mar 19 01:09:45 PM PDT 24
Finished Mar 19 01:36:00 PM PDT 24
Peak memory 387472 kb
Host smart-3d65a487-a34e-4b55-a3f4-35bc5113091a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=507731583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.507731583 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.3984493047
Short name T1015
Test name
Test status
Simulation time 70833583070 ps
CPU time 1387.63 seconds
Started Mar 19 01:09:43 PM PDT 24
Finished Mar 19 01:32:51 PM PDT 24
Peak memory 332100 kb
Host smart-08dfd03d-fba8-4afd-a0e9-ab3c73609102
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3984493047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.3984493047 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.3744206606
Short name T286
Test name
Test status
Simulation time 30494181399 ps
CPU time 813.76 seconds
Started Mar 19 01:09:44 PM PDT 24
Finished Mar 19 01:23:18 PM PDT 24
Peak memory 294144 kb
Host smart-10fb155a-ed34-40f3-a803-8b7120171f83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3744206606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.3744206606 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.2824411296
Short name T232
Test name
Test status
Simulation time 681509823720 ps
CPU time 4681.17 seconds
Started Mar 19 01:09:43 PM PDT 24
Finished Mar 19 02:27:45 PM PDT 24
Peak memory 641656 kb
Host smart-28416034-1b66-401e-a2e8-d7ae4096dfd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2824411296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.2824411296 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.433462562
Short name T1031
Test name
Test status
Simulation time 44792120939 ps
CPU time 3230.23 seconds
Started Mar 19 01:09:42 PM PDT 24
Finished Mar 19 02:03:33 PM PDT 24
Peak memory 564220 kb
Host smart-3a9eb465-0dc4-44bb-ae14-bcaf95a05496
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=433462562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.433462562 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.2672377560
Short name T471
Test name
Test status
Simulation time 19773893 ps
CPU time 0.82 seconds
Started Mar 19 01:10:11 PM PDT 24
Finished Mar 19 01:10:12 PM PDT 24
Peak memory 205348 kb
Host smart-ad5e39bc-839f-4e59-a262-cfdd58c150a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672377560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.2672377560 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.78199130
Short name T490
Test name
Test status
Simulation time 11222813899 ps
CPU time 105.84 seconds
Started Mar 19 01:10:03 PM PDT 24
Finished Mar 19 01:11:49 PM PDT 24
Peak memory 229756 kb
Host smart-0c4c4f31-c152-4cdf-b437-ca16c41f4eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78199130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.78199130 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.465442428
Short name T607
Test name
Test status
Simulation time 177083861367 ps
CPU time 715.64 seconds
Started Mar 19 01:09:54 PM PDT 24
Finished Mar 19 01:21:50 PM PDT 24
Peak memory 231752 kb
Host smart-84070c59-709f-43c8-856d-d96cccc15721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465442428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.465442428 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.2930318285
Short name T397
Test name
Test status
Simulation time 56711855030 ps
CPU time 272.08 seconds
Started Mar 19 01:10:02 PM PDT 24
Finished Mar 19 01:14:35 PM PDT 24
Peak memory 242656 kb
Host smart-4c08485b-7872-43d2-9eeb-e388e1758a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930318285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.2930318285 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.1775053387
Short name T96
Test name
Test status
Simulation time 4155892266 ps
CPU time 336.49 seconds
Started Mar 19 01:10:01 PM PDT 24
Finished Mar 19 01:15:38 PM PDT 24
Peak memory 250920 kb
Host smart-835547dd-47dd-4391-960c-9794d4fc3ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775053387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.1775053387 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.3991037390
Short name T653
Test name
Test status
Simulation time 622203749 ps
CPU time 2.61 seconds
Started Mar 19 01:10:03 PM PDT 24
Finished Mar 19 01:10:06 PM PDT 24
Peak memory 207552 kb
Host smart-00cd2ddf-8be9-461f-83cc-9fc82c1dd221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991037390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.3991037390 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.2714293170
Short name T9
Test name
Test status
Simulation time 54263780 ps
CPU time 1.44 seconds
Started Mar 19 01:10:03 PM PDT 24
Finished Mar 19 01:10:04 PM PDT 24
Peak memory 215964 kb
Host smart-57498275-4626-4604-9e28-9df347d2e0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714293170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.2714293170 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.2663428431
Short name T810
Test name
Test status
Simulation time 5496171747 ps
CPU time 178.87 seconds
Started Mar 19 01:09:53 PM PDT 24
Finished Mar 19 01:12:52 PM PDT 24
Peak memory 234220 kb
Host smart-393e4b2a-9db7-414c-9ff9-132cff652a94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663428431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.2663428431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.2393628525
Short name T478
Test name
Test status
Simulation time 14808009086 ps
CPU time 371.38 seconds
Started Mar 19 01:09:55 PM PDT 24
Finished Mar 19 01:16:06 PM PDT 24
Peak memory 247976 kb
Host smart-7331c38e-8897-40d6-9c2f-4be9e9227010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393628525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.2393628525 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.3459673753
Short name T264
Test name
Test status
Simulation time 7124275111 ps
CPU time 40.1 seconds
Started Mar 19 01:09:54 PM PDT 24
Finished Mar 19 01:10:34 PM PDT 24
Peak memory 218976 kb
Host smart-08b5d58e-c64c-46b8-8297-6fcc5588d3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459673753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.3459673753 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.2144908501
Short name T1033
Test name
Test status
Simulation time 145617659613 ps
CPU time 641.82 seconds
Started Mar 19 01:10:03 PM PDT 24
Finished Mar 19 01:20:45 PM PDT 24
Peak memory 321408 kb
Host smart-67561689-3dfc-4503-bb99-cc0d27904f1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2144908501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2144908501 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.3842488655
Short name T762
Test name
Test status
Simulation time 415079193 ps
CPU time 4.92 seconds
Started Mar 19 01:10:01 PM PDT 24
Finished Mar 19 01:10:06 PM PDT 24
Peak memory 215928 kb
Host smart-ee645b55-a1ab-4015-857d-d46d7c192256
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842488655 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.kmac_test_vectors_kmac.3842488655 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.3556999014
Short name T244
Test name
Test status
Simulation time 1278159187 ps
CPU time 4.21 seconds
Started Mar 19 01:10:03 PM PDT 24
Finished Mar 19 01:10:07 PM PDT 24
Peak memory 215900 kb
Host smart-c989f515-3e87-4552-86c1-9b1281f73356
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556999014 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.3556999014 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.3614225750
Short name T434
Test name
Test status
Simulation time 78206336372 ps
CPU time 1553.56 seconds
Started Mar 19 01:09:54 PM PDT 24
Finished Mar 19 01:35:48 PM PDT 24
Peak memory 391324 kb
Host smart-92501ebc-be90-4ffc-b681-fecbdc4babfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3614225750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.3614225750 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.1888541083
Short name T888
Test name
Test status
Simulation time 73120768317 ps
CPU time 1430.62 seconds
Started Mar 19 01:09:56 PM PDT 24
Finished Mar 19 01:33:46 PM PDT 24
Peak memory 370580 kb
Host smart-670b30dc-48b7-4bcd-b5ee-9b7b36035718
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1888541083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.1888541083 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.2311662964
Short name T509
Test name
Test status
Simulation time 46400592404 ps
CPU time 1171.51 seconds
Started Mar 19 01:10:03 PM PDT 24
Finished Mar 19 01:29:35 PM PDT 24
Peak memory 331732 kb
Host smart-b658d07d-de16-42db-9e47-df27f220d25d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2311662964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.2311662964 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.357776761
Short name T870
Test name
Test status
Simulation time 193431071444 ps
CPU time 980.09 seconds
Started Mar 19 01:10:03 PM PDT 24
Finished Mar 19 01:26:23 PM PDT 24
Peak memory 292684 kb
Host smart-fdee8fe8-3e44-455a-860f-1a7c925a1be7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=357776761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.357776761 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.3901982486
Short name T90
Test name
Test status
Simulation time 203996471930 ps
CPU time 4366.97 seconds
Started Mar 19 01:10:01 PM PDT 24
Finished Mar 19 02:22:49 PM PDT 24
Peak memory 653340 kb
Host smart-e6f59872-e8fc-44f5-8242-0bea243d3001
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3901982486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.3901982486 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.593441578
Short name T595
Test name
Test status
Simulation time 172934959219 ps
CPU time 3517.88 seconds
Started Mar 19 01:10:02 PM PDT 24
Finished Mar 19 02:08:40 PM PDT 24
Peak memory 560436 kb
Host smart-fc6a1186-c4a6-4452-ae74-94b1f2dac4bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=593441578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.593441578 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.2229725900
Short name T279
Test name
Test status
Simulation time 17356041 ps
CPU time 0.76 seconds
Started Mar 19 01:10:22 PM PDT 24
Finished Mar 19 01:10:23 PM PDT 24
Peak memory 205376 kb
Host smart-f4766172-2ba4-4cb6-adf5-6255fda4cfde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229725900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.2229725900 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.1513032990
Short name T652
Test name
Test status
Simulation time 33937678599 ps
CPU time 325.11 seconds
Started Mar 19 01:10:19 PM PDT 24
Finished Mar 19 01:15:45 PM PDT 24
Peak memory 244972 kb
Host smart-532359d1-2a16-4182-8a9f-a20301c8b0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513032990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.1513032990 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.3451303300
Short name T901
Test name
Test status
Simulation time 6225008071 ps
CPU time 515.27 seconds
Started Mar 19 01:10:11 PM PDT 24
Finished Mar 19 01:18:47 PM PDT 24
Peak memory 229968 kb
Host smart-19e7c5d5-bf79-4e39-bfa7-f580611f8b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451303300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3451303300 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.3151520793
Short name T1046
Test name
Test status
Simulation time 3236114611 ps
CPU time 25.71 seconds
Started Mar 19 01:10:19 PM PDT 24
Finished Mar 19 01:10:45 PM PDT 24
Peak memory 224084 kb
Host smart-fb30e47a-a82d-4f99-8251-a8856660e1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151520793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.3151520793 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.4267252907
Short name T897
Test name
Test status
Simulation time 15013940346 ps
CPU time 96.72 seconds
Started Mar 19 01:10:20 PM PDT 24
Finished Mar 19 01:11:56 PM PDT 24
Peak memory 238172 kb
Host smart-a46f43c4-da0e-46cb-8e0d-fac8a3b79176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267252907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.4267252907 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.3503491170
Short name T773
Test name
Test status
Simulation time 469926997 ps
CPU time 1.99 seconds
Started Mar 19 01:10:20 PM PDT 24
Finished Mar 19 01:10:22 PM PDT 24
Peak memory 207360 kb
Host smart-d55233ba-5d2b-444c-9f93-f91f3976b71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503491170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.3503491170 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.2373599513
Short name T759
Test name
Test status
Simulation time 88310559 ps
CPU time 1.39 seconds
Started Mar 19 01:10:21 PM PDT 24
Finished Mar 19 01:10:23 PM PDT 24
Peak memory 215736 kb
Host smart-8deda99a-a9f8-45ee-bcfe-87477066d43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373599513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.2373599513 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.4096335058
Short name T646
Test name
Test status
Simulation time 13297374338 ps
CPU time 1044.96 seconds
Started Mar 19 01:10:12 PM PDT 24
Finished Mar 19 01:27:37 PM PDT 24
Peak memory 335076 kb
Host smart-d5beaca9-bcab-415a-aed7-736c06decbbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096335058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.4096335058 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.1159729147
Short name T750
Test name
Test status
Simulation time 17103690667 ps
CPU time 331.35 seconds
Started Mar 19 01:10:13 PM PDT 24
Finished Mar 19 01:15:45 PM PDT 24
Peak memory 247792 kb
Host smart-3da66190-7ada-499c-8969-3bcfb82d79c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159729147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1159729147 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.1537030853
Short name T915
Test name
Test status
Simulation time 33530392545 ps
CPU time 64.09 seconds
Started Mar 19 01:10:11 PM PDT 24
Finished Mar 19 01:11:15 PM PDT 24
Peak memory 224156 kb
Host smart-7bece7ec-d1d2-4712-a399-364bf6bf4fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537030853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.1537030853 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.2293402409
Short name T728
Test name
Test status
Simulation time 695439670894 ps
CPU time 1847.31 seconds
Started Mar 19 01:10:20 PM PDT 24
Finished Mar 19 01:41:07 PM PDT 24
Peak memory 425440 kb
Host smart-e74a895b-624b-4b92-a5d8-190aa885f4d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2293402409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.2293402409 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.1669672010
Short name T617
Test name
Test status
Simulation time 132928999 ps
CPU time 4.04 seconds
Started Mar 19 01:10:20 PM PDT 24
Finished Mar 19 01:10:24 PM PDT 24
Peak memory 215956 kb
Host smart-2bb90d5a-b775-41fe-be9d-9031fa84cb01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669672010 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac.1669672010 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.389884823
Short name T316
Test name
Test status
Simulation time 311443325 ps
CPU time 3.91 seconds
Started Mar 19 01:10:19 PM PDT 24
Finished Mar 19 01:10:23 PM PDT 24
Peak memory 215824 kb
Host smart-a1064101-28fa-4fb1-9d5f-4130351a48e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389884823 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.kmac_test_vectors_kmac_xof.389884823 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.913230501
Short name T1008
Test name
Test status
Simulation time 100493603676 ps
CPU time 1829.01 seconds
Started Mar 19 01:10:13 PM PDT 24
Finished Mar 19 01:40:43 PM PDT 24
Peak memory 389216 kb
Host smart-08ca103d-9796-436a-83ba-de1315d59a4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=913230501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.913230501 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.3992414744
Short name T662
Test name
Test status
Simulation time 440726204690 ps
CPU time 1782.64 seconds
Started Mar 19 01:10:13 PM PDT 24
Finished Mar 19 01:39:57 PM PDT 24
Peak memory 377648 kb
Host smart-7c4e00c4-ba78-4691-8131-955585fe903a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3992414744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.3992414744 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.621791482
Short name T857
Test name
Test status
Simulation time 284605948059 ps
CPU time 1363.71 seconds
Started Mar 19 01:10:10 PM PDT 24
Finished Mar 19 01:32:55 PM PDT 24
Peak memory 342976 kb
Host smart-de947e9f-ce7f-48b3-a2fb-dc6200043d3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=621791482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.621791482 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.810688421
Short name T241
Test name
Test status
Simulation time 40260102516 ps
CPU time 773.57 seconds
Started Mar 19 01:10:11 PM PDT 24
Finished Mar 19 01:23:05 PM PDT 24
Peak memory 298548 kb
Host smart-f3c1acba-0868-4195-a415-6377e8a7511b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=810688421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.810688421 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.528778811
Short name T825
Test name
Test status
Simulation time 50254811824 ps
CPU time 3683.14 seconds
Started Mar 19 01:10:10 PM PDT 24
Finished Mar 19 02:11:34 PM PDT 24
Peak memory 639032 kb
Host smart-c7caecc1-18b9-475d-9b93-2df8ee57161e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=528778811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.528778811 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.649937557
Short name T538
Test name
Test status
Simulation time 44973930512 ps
CPU time 3429.67 seconds
Started Mar 19 01:10:13 PM PDT 24
Finished Mar 19 02:07:23 PM PDT 24
Peak memory 569136 kb
Host smart-14bcae33-01b2-491d-a3dd-fe72373e755e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=649937557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.649937557 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.4267573391
Short name T419
Test name
Test status
Simulation time 13368537 ps
CPU time 0.82 seconds
Started Mar 19 01:10:44 PM PDT 24
Finished Mar 19 01:10:44 PM PDT 24
Peak memory 205276 kb
Host smart-1232c791-e3c1-446c-b1cf-aac7175ffcf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267573391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.4267573391 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.1100521984
Short name T250
Test name
Test status
Simulation time 32860726369 ps
CPU time 176.89 seconds
Started Mar 19 01:10:35 PM PDT 24
Finished Mar 19 01:13:32 PM PDT 24
Peak memory 233172 kb
Host smart-034a4406-1bbb-4e5d-8db3-8e599e9969d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100521984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1100521984 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.872814924
Short name T904
Test name
Test status
Simulation time 783448547 ps
CPU time 7.34 seconds
Started Mar 19 01:10:26 PM PDT 24
Finished Mar 19 01:10:34 PM PDT 24
Peak memory 220420 kb
Host smart-7fc2ce84-828d-4c10-b410-fa790e2948f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872814924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.872814924 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.1926180622
Short name T265
Test name
Test status
Simulation time 11736549034 ps
CPU time 88.14 seconds
Started Mar 19 01:10:42 PM PDT 24
Finished Mar 19 01:12:10 PM PDT 24
Peak memory 228296 kb
Host smart-ff3770ba-f440-4e51-b567-0429d272c439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926180622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.1926180622 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.1975111424
Short name T154
Test name
Test status
Simulation time 20463593515 ps
CPU time 199.04 seconds
Started Mar 19 01:10:43 PM PDT 24
Finished Mar 19 01:14:03 PM PDT 24
Peak memory 248696 kb
Host smart-605f3245-e7c3-42a9-98f7-d29e9d6b1c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975111424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.1975111424 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.318805647
Short name T721
Test name
Test status
Simulation time 675391253 ps
CPU time 3.78 seconds
Started Mar 19 01:10:43 PM PDT 24
Finished Mar 19 01:10:47 PM PDT 24
Peak memory 207140 kb
Host smart-425f6cb1-b16b-4fb6-b199-a32f603a4e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318805647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.318805647 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.1352500200
Short name T354
Test name
Test status
Simulation time 38430695 ps
CPU time 1.44 seconds
Started Mar 19 01:10:45 PM PDT 24
Finished Mar 19 01:10:47 PM PDT 24
Peak memory 217468 kb
Host smart-c5ba2a7f-b197-4c0b-91fb-9639c81ec285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352500200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.1352500200 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.489536323
Short name T428
Test name
Test status
Simulation time 17965711082 ps
CPU time 1486.55 seconds
Started Mar 19 01:10:27 PM PDT 24
Finished Mar 19 01:35:14 PM PDT 24
Peak memory 377360 kb
Host smart-e3e1d1b9-50a3-4bd5-a056-89d2f93b521b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489536323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_an
d_output.489536323 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.3800458280
Short name T932
Test name
Test status
Simulation time 7017069063 ps
CPU time 274.82 seconds
Started Mar 19 01:10:27 PM PDT 24
Finished Mar 19 01:15:02 PM PDT 24
Peak memory 242352 kb
Host smart-c6d0e1ee-e05d-4116-87ad-d08ed0ff7c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800458280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.3800458280 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.698782664
Short name T535
Test name
Test status
Simulation time 2246315367 ps
CPU time 24.89 seconds
Started Mar 19 01:10:19 PM PDT 24
Finished Mar 19 01:10:44 PM PDT 24
Peak memory 219672 kb
Host smart-9f6735dc-69b8-497a-b3e7-5d03e1dfdadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698782664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.698782664 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.3041417045
Short name T387
Test name
Test status
Simulation time 29915258048 ps
CPU time 223.37 seconds
Started Mar 19 01:10:41 PM PDT 24
Finished Mar 19 01:14:25 PM PDT 24
Peak memory 238796 kb
Host smart-7bcdb5d3-73f2-4b0a-b18b-b429c596db28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3041417045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.3041417045 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.2971808927
Short name T703
Test name
Test status
Simulation time 163545024 ps
CPU time 4 seconds
Started Mar 19 01:10:26 PM PDT 24
Finished Mar 19 01:10:31 PM PDT 24
Peak memory 215984 kb
Host smart-ba7e06b9-2d5c-4bae-a0e1-d65652d077c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971808927 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.2971808927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.3559196874
Short name T663
Test name
Test status
Simulation time 211125078 ps
CPU time 4.08 seconds
Started Mar 19 01:10:34 PM PDT 24
Finished Mar 19 01:10:38 PM PDT 24
Peak memory 215972 kb
Host smart-02213033-d189-4129-9b7b-760ab9ae678f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559196874 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.3559196874 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.17420405
Short name T350
Test name
Test status
Simulation time 19161474684 ps
CPU time 1527.97 seconds
Started Mar 19 01:10:27 PM PDT 24
Finished Mar 19 01:35:55 PM PDT 24
Peak memory 398160 kb
Host smart-7d15a22c-a469-4739-b482-03489573179b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=17420405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.17420405 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.3144148984
Short name T1027
Test name
Test status
Simulation time 23689202470 ps
CPU time 1442.26 seconds
Started Mar 19 01:10:28 PM PDT 24
Finished Mar 19 01:34:31 PM PDT 24
Peak memory 374948 kb
Host smart-ffda9fe2-e28a-42eb-88c6-c7da4da6b728
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3144148984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.3144148984 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.117377675
Short name T811
Test name
Test status
Simulation time 312506543172 ps
CPU time 1438.87 seconds
Started Mar 19 01:10:25 PM PDT 24
Finished Mar 19 01:34:25 PM PDT 24
Peak memory 334976 kb
Host smart-c12f83b6-da7d-4d17-bc5c-b306e82c8dd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=117377675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.117377675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.2791018175
Short name T554
Test name
Test status
Simulation time 129993774359 ps
CPU time 861.04 seconds
Started Mar 19 01:10:26 PM PDT 24
Finished Mar 19 01:24:48 PM PDT 24
Peak memory 293644 kb
Host smart-722fb4dc-0950-4527-bee9-32ffd9934512
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2791018175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.2791018175 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.2143050344
Short name T231
Test name
Test status
Simulation time 91160155499 ps
CPU time 4429.52 seconds
Started Mar 19 01:10:26 PM PDT 24
Finished Mar 19 02:24:16 PM PDT 24
Peak memory 654680 kb
Host smart-a0ea1ae6-0e4d-4734-942a-cfcfc9233ca9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2143050344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.2143050344 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.3047097163
Short name T280
Test name
Test status
Simulation time 431053351886 ps
CPU time 4771.78 seconds
Started Mar 19 01:10:27 PM PDT 24
Finished Mar 19 02:30:00 PM PDT 24
Peak memory 572972 kb
Host smart-bb546000-d509-4342-95d2-d6d093bc55dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3047097163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.3047097163 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.2116275883
Short name T555
Test name
Test status
Simulation time 30738599 ps
CPU time 0.75 seconds
Started Mar 19 01:11:09 PM PDT 24
Finished Mar 19 01:11:10 PM PDT 24
Peak memory 205404 kb
Host smart-93b41bc7-f1e9-492a-9597-37fc175e124b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116275883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.2116275883 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.3783011440
Short name T869
Test name
Test status
Simulation time 3854787418 ps
CPU time 94.1 seconds
Started Mar 19 01:11:10 PM PDT 24
Finished Mar 19 01:12:44 PM PDT 24
Peak memory 230684 kb
Host smart-88f8f1f7-901c-4e56-93a5-e97345009dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783011440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.3783011440 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.2192504053
Short name T988
Test name
Test status
Simulation time 61281398474 ps
CPU time 129.67 seconds
Started Mar 19 01:10:43 PM PDT 24
Finished Mar 19 01:12:53 PM PDT 24
Peak memory 223240 kb
Host smart-0cb6e6f2-6f15-4a17-8654-703a6f681fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192504053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.2192504053 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.1107942796
Short name T42
Test name
Test status
Simulation time 1155212922 ps
CPU time 24.22 seconds
Started Mar 19 01:11:09 PM PDT 24
Finished Mar 19 01:11:33 PM PDT 24
Peak memory 224096 kb
Host smart-ecefd986-3c62-4a02-8900-b5498519d7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107942796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1107942796 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.783879308
Short name T600
Test name
Test status
Simulation time 45865039214 ps
CPU time 164.09 seconds
Started Mar 19 01:11:07 PM PDT 24
Finished Mar 19 01:13:51 PM PDT 24
Peak memory 256764 kb
Host smart-c1ad248f-d646-4b51-8d89-199f104b9731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783879308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.783879308 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.4272586759
Short name T267
Test name
Test status
Simulation time 628072523 ps
CPU time 3.99 seconds
Started Mar 19 01:11:09 PM PDT 24
Finished Mar 19 01:11:13 PM PDT 24
Peak memory 207568 kb
Host smart-70048e61-7a48-4ab8-8b88-69f49bab37d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272586759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.4272586759 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.3296223652
Short name T803
Test name
Test status
Simulation time 46996367610 ps
CPU time 1012.74 seconds
Started Mar 19 01:10:45 PM PDT 24
Finished Mar 19 01:27:38 PM PDT 24
Peak memory 323504 kb
Host smart-8afd7c33-0ac8-4615-b6ea-e36c3056f72d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296223652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.3296223652 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.3376938944
Short name T342
Test name
Test status
Simulation time 3585517427 ps
CPU time 143.32 seconds
Started Mar 19 01:10:43 PM PDT 24
Finished Mar 19 01:13:07 PM PDT 24
Peak memory 235620 kb
Host smart-50ba6604-171c-49a3-b04b-3fa77f2c679f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376938944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.3376938944 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.849145670
Short name T700
Test name
Test status
Simulation time 3215265193 ps
CPU time 42.82 seconds
Started Mar 19 01:10:43 PM PDT 24
Finished Mar 19 01:11:26 PM PDT 24
Peak memory 224124 kb
Host smart-949ef5d0-111f-41bd-82f1-17749742ee0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849145670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.849145670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.3330658613
Short name T919
Test name
Test status
Simulation time 16880160787 ps
CPU time 1089.97 seconds
Started Mar 19 01:11:10 PM PDT 24
Finished Mar 19 01:29:21 PM PDT 24
Peak memory 347436 kb
Host smart-fb273ee4-75ef-4484-ac99-4e56f6e57a32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3330658613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.3330658613 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.1510127568
Short name T514
Test name
Test status
Simulation time 1171163620 ps
CPU time 5.34 seconds
Started Mar 19 01:11:09 PM PDT 24
Finished Mar 19 01:11:14 PM PDT 24
Peak memory 209008 kb
Host smart-84065176-14b4-443f-b497-d424bdea770a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510127568 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.kmac_test_vectors_kmac.1510127568 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.4075890078
Short name T959
Test name
Test status
Simulation time 535137615 ps
CPU time 5.18 seconds
Started Mar 19 01:11:05 PM PDT 24
Finished Mar 19 01:11:11 PM PDT 24
Peak memory 216012 kb
Host smart-5205aab6-d34c-485e-b29c-c8039e31f70f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075890078 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.4075890078 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.2929167246
Short name T1079
Test name
Test status
Simulation time 19150801139 ps
CPU time 1463.13 seconds
Started Mar 19 01:10:56 PM PDT 24
Finished Mar 19 01:35:19 PM PDT 24
Peak memory 376224 kb
Host smart-702f44fe-e7cd-409b-81f9-1ae19883c743
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2929167246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.2929167246 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.2807761971
Short name T623
Test name
Test status
Simulation time 606467634235 ps
CPU time 1711.05 seconds
Started Mar 19 01:10:55 PM PDT 24
Finished Mar 19 01:39:27 PM PDT 24
Peak memory 371752 kb
Host smart-c58d2fef-3975-4bbe-a74b-2d5cc76c5307
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2807761971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.2807761971 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.926958957
Short name T207
Test name
Test status
Simulation time 297156751807 ps
CPU time 1257.65 seconds
Started Mar 19 01:10:55 PM PDT 24
Finished Mar 19 01:31:53 PM PDT 24
Peak memory 338284 kb
Host smart-6ef3961f-e467-4436-bbda-5c6faad26431
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=926958957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.926958957 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.553955763
Short name T317
Test name
Test status
Simulation time 51020889737 ps
CPU time 976.99 seconds
Started Mar 19 01:10:55 PM PDT 24
Finished Mar 19 01:27:12 PM PDT 24
Peak memory 293764 kb
Host smart-aafd7b20-bd1d-4463-b6a6-55d11edfdb74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=553955763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.553955763 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.1852886224
Short name T275
Test name
Test status
Simulation time 519111156624 ps
CPU time 5389.99 seconds
Started Mar 19 01:10:53 PM PDT 24
Finished Mar 19 02:40:44 PM PDT 24
Peak memory 661012 kb
Host smart-b863f91e-61c6-43a1-924e-a238aad24857
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1852886224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.1852886224 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.265722328
Short name T1061
Test name
Test status
Simulation time 578847907364 ps
CPU time 4022.63 seconds
Started Mar 19 01:11:07 PM PDT 24
Finished Mar 19 02:18:10 PM PDT 24
Peak memory 558932 kb
Host smart-3ee34ece-b2dc-4186-a914-9761a6b1e1ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=265722328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.265722328 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.2858924215
Short name T311
Test name
Test status
Simulation time 29461575 ps
CPU time 0.76 seconds
Started Mar 19 01:11:22 PM PDT 24
Finished Mar 19 01:11:23 PM PDT 24
Peak memory 205316 kb
Host smart-67da1cdc-83e7-4065-b567-8caa1587baaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858924215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.2858924215 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.4166295328
Short name T309
Test name
Test status
Simulation time 64609383915 ps
CPU time 310.75 seconds
Started Mar 19 01:11:17 PM PDT 24
Finished Mar 19 01:16:28 PM PDT 24
Peak memory 243404 kb
Host smart-2e7df1ca-6bcb-4293-9b7a-c014774947c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166295328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.4166295328 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.1214519276
Short name T693
Test name
Test status
Simulation time 939968138 ps
CPU time 68.01 seconds
Started Mar 19 01:11:10 PM PDT 24
Finished Mar 19 01:12:18 PM PDT 24
Peak memory 224136 kb
Host smart-477225b0-af8f-413f-b82c-fc33c777bb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214519276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.1214519276 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.1396454684
Short name T833
Test name
Test status
Simulation time 19964713911 ps
CPU time 172.57 seconds
Started Mar 19 01:11:17 PM PDT 24
Finished Mar 19 01:14:10 PM PDT 24
Peak memory 236528 kb
Host smart-2cb4f77e-2984-400e-8a51-d4e41c93620d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396454684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.1396454684 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.1310004177
Short name T920
Test name
Test status
Simulation time 10557074476 ps
CPU time 148.79 seconds
Started Mar 19 01:11:19 PM PDT 24
Finished Mar 19 01:13:48 PM PDT 24
Peak memory 252156 kb
Host smart-c9e7a4b2-0429-4e20-835b-3ff348839a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310004177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.1310004177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.276480684
Short name T256
Test name
Test status
Simulation time 3662830004 ps
CPU time 2.82 seconds
Started Mar 19 01:11:15 PM PDT 24
Finished Mar 19 01:11:18 PM PDT 24
Peak memory 207724 kb
Host smart-e7cfe8f7-cb9b-4104-a4e8-dfc4c9144c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276480684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.276480684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.903612700
Short name T57
Test name
Test status
Simulation time 42404360 ps
CPU time 1.18 seconds
Started Mar 19 01:11:21 PM PDT 24
Finished Mar 19 01:11:23 PM PDT 24
Peak memory 215804 kb
Host smart-88b256ef-dc18-4fcf-85ab-a2371d3affbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903612700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.903612700 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.2668068379
Short name T524
Test name
Test status
Simulation time 386572001251 ps
CPU time 2107.12 seconds
Started Mar 19 01:11:06 PM PDT 24
Finished Mar 19 01:46:14 PM PDT 24
Peak memory 406268 kb
Host smart-e2df3801-b329-4b37-a537-7e959d3d149c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668068379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.2668068379 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.3879700480
Short name T769
Test name
Test status
Simulation time 3642851276 ps
CPU time 52.09 seconds
Started Mar 19 01:11:08 PM PDT 24
Finished Mar 19 01:12:01 PM PDT 24
Peak memory 224104 kb
Host smart-5040f9ed-44c1-42e8-93be-d9c649cdbc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879700480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.3879700480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.2001945288
Short name T319
Test name
Test status
Simulation time 2187258481 ps
CPU time 4.68 seconds
Started Mar 19 01:11:06 PM PDT 24
Finished Mar 19 01:11:11 PM PDT 24
Peak memory 220884 kb
Host smart-e0ee09b1-5aec-44eb-9263-6f4b1f6eb2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001945288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2001945288 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.1958233026
Short name T914
Test name
Test status
Simulation time 263412902 ps
CPU time 3.86 seconds
Started Mar 19 01:11:15 PM PDT 24
Finished Mar 19 01:11:20 PM PDT 24
Peak memory 215988 kb
Host smart-5e9f74a9-f125-487c-9b17-e82c3d36ec3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1958233026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1958233026 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.257738768
Short name T494
Test name
Test status
Simulation time 277341244 ps
CPU time 5.34 seconds
Started Mar 19 01:11:21 PM PDT 24
Finished Mar 19 01:11:26 PM PDT 24
Peak memory 215852 kb
Host smart-65bbd315-b30f-44b9-aa39-dd3d56ea4604
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257738768 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.kmac_test_vectors_kmac.257738768 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.783457835
Short name T960
Test name
Test status
Simulation time 998874176 ps
CPU time 4.52 seconds
Started Mar 19 01:11:20 PM PDT 24
Finished Mar 19 01:11:25 PM PDT 24
Peak memory 215904 kb
Host smart-48442718-9c23-4d03-9613-c22f68f46175
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783457835 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.kmac_test_vectors_kmac_xof.783457835 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.4009708396
Short name T230
Test name
Test status
Simulation time 361257966391 ps
CPU time 1753.47 seconds
Started Mar 19 01:11:09 PM PDT 24
Finished Mar 19 01:40:23 PM PDT 24
Peak memory 387436 kb
Host smart-e4df3184-8360-47b7-baac-3c179d040afc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4009708396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.4009708396 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.608457996
Short name T495
Test name
Test status
Simulation time 73119476109 ps
CPU time 1485.59 seconds
Started Mar 19 01:11:07 PM PDT 24
Finished Mar 19 01:35:53 PM PDT 24
Peak memory 369616 kb
Host smart-7decc714-3458-4f65-9766-cbb7723bc6af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=608457996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.608457996 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.2608430409
Short name T336
Test name
Test status
Simulation time 146277714453 ps
CPU time 1299.41 seconds
Started Mar 19 01:11:19 PM PDT 24
Finished Mar 19 01:32:59 PM PDT 24
Peak memory 340908 kb
Host smart-f6d4159b-a104-4acc-b54a-b1f70cd44469
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2608430409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.2608430409 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.2035740036
Short name T827
Test name
Test status
Simulation time 43697921130 ps
CPU time 861.48 seconds
Started Mar 19 01:11:18 PM PDT 24
Finished Mar 19 01:25:39 PM PDT 24
Peak memory 291752 kb
Host smart-55b3d25f-9989-4f78-86a9-1e3eb4e5ec4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2035740036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.2035740036 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.1744028261
Short name T699
Test name
Test status
Simulation time 717542772690 ps
CPU time 4954.67 seconds
Started Mar 19 01:11:16 PM PDT 24
Finished Mar 19 02:33:52 PM PDT 24
Peak memory 651720 kb
Host smart-cdb4e949-7543-439d-8e4d-6f18c36a9d04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1744028261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.1744028261 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.1081471162
Short name T635
Test name
Test status
Simulation time 537075817123 ps
CPU time 3305.64 seconds
Started Mar 19 01:11:15 PM PDT 24
Finished Mar 19 02:06:22 PM PDT 24
Peak memory 553664 kb
Host smart-92310de1-9edc-411f-a433-d4d7d710b89b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1081471162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.1081471162 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.531855131
Short name T450
Test name
Test status
Simulation time 51279762 ps
CPU time 0.82 seconds
Started Mar 19 01:11:40 PM PDT 24
Finished Mar 19 01:11:42 PM PDT 24
Peak memory 205364 kb
Host smart-3483ed10-a92e-4aa0-9fe1-b7a533d9c491
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531855131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.531855131 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.3434298507
Short name T457
Test name
Test status
Simulation time 101342966 ps
CPU time 3.04 seconds
Started Mar 19 01:11:29 PM PDT 24
Finished Mar 19 01:11:32 PM PDT 24
Peak memory 218760 kb
Host smart-236d5058-c055-4be0-9991-3883300be904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434298507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.3434298507 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.2307270660
Short name T879
Test name
Test status
Simulation time 3114898392 ps
CPU time 71.43 seconds
Started Mar 19 01:11:21 PM PDT 24
Finished Mar 19 01:12:33 PM PDT 24
Peak memory 224136 kb
Host smart-2652398d-3b16-487c-b2ef-f48fde78ef38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307270660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.2307270660 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.908072274
Short name T261
Test name
Test status
Simulation time 33038611205 ps
CPU time 307.99 seconds
Started Mar 19 01:11:30 PM PDT 24
Finished Mar 19 01:16:38 PM PDT 24
Peak memory 246308 kb
Host smart-9a10284d-7fab-4092-81a8-70b65be4eda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908072274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.908072274 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.1174765494
Short name T455
Test name
Test status
Simulation time 9750084386 ps
CPU time 42.48 seconds
Started Mar 19 01:11:29 PM PDT 24
Finished Mar 19 01:12:12 PM PDT 24
Peak memory 240208 kb
Host smart-461e77d9-d221-4032-97b8-2e3728f2bd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174765494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.1174765494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.3504191980
Short name T22
Test name
Test status
Simulation time 52936047 ps
CPU time 1.12 seconds
Started Mar 19 01:11:39 PM PDT 24
Finished Mar 19 01:11:41 PM PDT 24
Peak memory 206772 kb
Host smart-5ab01190-4e09-4836-a666-ab2f6dee9b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504191980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.3504191980 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.246586165
Short name T58
Test name
Test status
Simulation time 132512871 ps
CPU time 1.36 seconds
Started Mar 19 01:11:43 PM PDT 24
Finished Mar 19 01:11:44 PM PDT 24
Peak memory 215952 kb
Host smart-ca832fc1-7c21-4f42-b959-eac894dbb4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246586165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.246586165 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.4151860775
Short name T481
Test name
Test status
Simulation time 75660507370 ps
CPU time 2229.09 seconds
Started Mar 19 01:11:23 PM PDT 24
Finished Mar 19 01:48:33 PM PDT 24
Peak memory 435148 kb
Host smart-a924c11d-d3d0-43be-a872-615e3f67a2b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151860775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.4151860775 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.1008664491
Short name T927
Test name
Test status
Simulation time 10099883772 ps
CPU time 261.57 seconds
Started Mar 19 01:11:22 PM PDT 24
Finished Mar 19 01:15:43 PM PDT 24
Peak memory 241716 kb
Host smart-18da8873-9318-4b76-b807-3d3f0e660c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008664491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.1008664491 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.2792061197
Short name T976
Test name
Test status
Simulation time 4080483095 ps
CPU time 21.69 seconds
Started Mar 19 01:11:23 PM PDT 24
Finished Mar 19 01:11:45 PM PDT 24
Peak memory 219056 kb
Host smart-4292adb4-0d9c-43b6-aa34-3fb891979317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792061197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.2792061197 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.2448425333
Short name T258
Test name
Test status
Simulation time 10167509522 ps
CPU time 208.26 seconds
Started Mar 19 01:11:40 PM PDT 24
Finished Mar 19 01:15:09 PM PDT 24
Peak memory 240500 kb
Host smart-c5313abf-331e-43ee-a31d-eb902d5cb31d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2448425333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.2448425333 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.284845632
Short name T68
Test name
Test status
Simulation time 866389529 ps
CPU time 4.73 seconds
Started Mar 19 01:11:22 PM PDT 24
Finished Mar 19 01:11:27 PM PDT 24
Peak memory 215864 kb
Host smart-5fa348c5-b3ed-4afb-97fd-25814f55a3a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284845632 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.kmac_test_vectors_kmac.284845632 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.3472440037
Short name T210
Test name
Test status
Simulation time 263883252 ps
CPU time 5.17 seconds
Started Mar 19 01:11:30 PM PDT 24
Finished Mar 19 01:11:35 PM PDT 24
Peak memory 215936 kb
Host smart-4b25e6ab-0f52-4aaa-a103-6cc569d3c4cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472440037 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.3472440037 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.3251324094
Short name T242
Test name
Test status
Simulation time 1278818058769 ps
CPU time 2290.35 seconds
Started Mar 19 01:11:27 PM PDT 24
Finished Mar 19 01:49:37 PM PDT 24
Peak memory 379348 kb
Host smart-57d0b383-cdd1-4cf7-af9f-dd30a0549296
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3251324094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.3251324094 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.4082729097
Short name T197
Test name
Test status
Simulation time 60252605531 ps
CPU time 1705.18 seconds
Started Mar 19 01:11:19 PM PDT 24
Finished Mar 19 01:39:45 PM PDT 24
Peak memory 369680 kb
Host smart-5e60703e-f1f2-428b-ad09-f20d8e3fa61c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4082729097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.4082729097 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.2503700955
Short name T757
Test name
Test status
Simulation time 72161311544 ps
CPU time 1353.54 seconds
Started Mar 19 01:11:23 PM PDT 24
Finished Mar 19 01:33:57 PM PDT 24
Peak memory 337304 kb
Host smart-1fe6cb4c-66de-4c09-8a8d-ba2b2a59964f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2503700955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.2503700955 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.2019773786
Short name T676
Test name
Test status
Simulation time 189197257304 ps
CPU time 983.31 seconds
Started Mar 19 01:11:23 PM PDT 24
Finished Mar 19 01:27:46 PM PDT 24
Peak memory 295840 kb
Host smart-e0a40aa5-85fa-4335-b574-ef46d3233656
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2019773786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.2019773786 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.4051546295
Short name T862
Test name
Test status
Simulation time 253925176905 ps
CPU time 5144.61 seconds
Started Mar 19 01:11:23 PM PDT 24
Finished Mar 19 02:37:09 PM PDT 24
Peak memory 639528 kb
Host smart-a4cfdf43-66c6-4e48-be30-7667b69aaa67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4051546295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.4051546295 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_alert_test.2909218015
Short name T48
Test name
Test status
Simulation time 15688151 ps
CPU time 0.75 seconds
Started Mar 19 01:11:58 PM PDT 24
Finished Mar 19 01:11:59 PM PDT 24
Peak memory 205408 kb
Host smart-e59e3ea8-83d0-4572-b1fa-dc48c1627f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909218015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.2909218015 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.3021391209
Short name T547
Test name
Test status
Simulation time 13365388700 ps
CPU time 328.16 seconds
Started Mar 19 01:12:01 PM PDT 24
Finished Mar 19 01:17:29 PM PDT 24
Peak memory 247608 kb
Host smart-b8129d71-c4ac-41a1-8739-28aa1de1dbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021391209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.3021391209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.2473867861
Short name T133
Test name
Test status
Simulation time 77202555807 ps
CPU time 825.64 seconds
Started Mar 19 01:11:49 PM PDT 24
Finished Mar 19 01:25:35 PM PDT 24
Peak memory 232052 kb
Host smart-042014bc-9916-4a1e-8786-f334b71dbb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473867861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.2473867861 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.2757719957
Short name T924
Test name
Test status
Simulation time 2340478102 ps
CPU time 22.04 seconds
Started Mar 19 01:11:58 PM PDT 24
Finished Mar 19 01:12:20 PM PDT 24
Peak memory 220996 kb
Host smart-6d6b657a-e5dc-4646-b441-b4fc6ead9a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757719957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.2757719957 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_key_error.993496589
Short name T941
Test name
Test status
Simulation time 403995745 ps
CPU time 1.09 seconds
Started Mar 19 01:11:58 PM PDT 24
Finished Mar 19 01:12:00 PM PDT 24
Peak memory 205632 kb
Host smart-04966554-7c30-45e9-8d3a-9dd2d6071225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993496589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.993496589 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.1408647294
Short name T37
Test name
Test status
Simulation time 63442908 ps
CPU time 1.24 seconds
Started Mar 19 01:11:57 PM PDT 24
Finished Mar 19 01:11:59 PM PDT 24
Peak memory 216092 kb
Host smart-a70039f3-891c-41bb-aedb-fd34d23f93a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408647294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.1408647294 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.2472694008
Short name T630
Test name
Test status
Simulation time 7604880412 ps
CPU time 620.4 seconds
Started Mar 19 01:11:49 PM PDT 24
Finished Mar 19 01:22:09 PM PDT 24
Peak memory 288668 kb
Host smart-d4e864af-523c-4196-9738-5841f34e1b84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472694008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.2472694008 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.1678538883
Short name T395
Test name
Test status
Simulation time 2331937477 ps
CPU time 7.98 seconds
Started Mar 19 01:11:48 PM PDT 24
Finished Mar 19 01:11:56 PM PDT 24
Peak memory 220316 kb
Host smart-d7a3fac3-d1ca-4802-a863-56b4f4f3c42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678538883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.1678538883 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.4170227746
Short name T877
Test name
Test status
Simulation time 260506051 ps
CPU time 12.72 seconds
Started Mar 19 01:11:48 PM PDT 24
Finished Mar 19 01:12:00 PM PDT 24
Peak memory 217988 kb
Host smart-78d07af5-34c8-46d7-a0cd-db0055522550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170227746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.4170227746 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.2423760866
Short name T567
Test name
Test status
Simulation time 3556734719 ps
CPU time 13.47 seconds
Started Mar 19 01:11:59 PM PDT 24
Finished Mar 19 01:12:13 PM PDT 24
Peak memory 221532 kb
Host smart-f6df8b1b-7901-4431-b2be-aee166f973a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2423760866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.2423760866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.456714659
Short name T1001
Test name
Test status
Simulation time 64204894 ps
CPU time 4.22 seconds
Started Mar 19 01:12:02 PM PDT 24
Finished Mar 19 01:12:07 PM PDT 24
Peak memory 215940 kb
Host smart-31a1a8d0-36ca-4f6e-b1e5-bdce0022057d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456714659 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.kmac_test_vectors_kmac.456714659 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.3586299112
Short name T804
Test name
Test status
Simulation time 265555593 ps
CPU time 4.27 seconds
Started Mar 19 01:11:57 PM PDT 24
Finished Mar 19 01:12:02 PM PDT 24
Peak memory 209416 kb
Host smart-7509d748-94c4-46c9-8584-0ebe300a7698
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586299112 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.3586299112 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.564981292
Short name T407
Test name
Test status
Simulation time 70922688241 ps
CPU time 1542.65 seconds
Started Mar 19 01:11:51 PM PDT 24
Finished Mar 19 01:37:34 PM PDT 24
Peak memory 377016 kb
Host smart-82bdc891-9f65-482e-90f2-7c095e0aefd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=564981292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.564981292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.225686483
Short name T559
Test name
Test status
Simulation time 127478760108 ps
CPU time 1842.67 seconds
Started Mar 19 01:11:47 PM PDT 24
Finished Mar 19 01:42:30 PM PDT 24
Peak memory 374684 kb
Host smart-fb5e9098-2e11-4cb6-b303-90759325b133
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=225686483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.225686483 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.206168143
Short name T1074
Test name
Test status
Simulation time 54897229071 ps
CPU time 1159.95 seconds
Started Mar 19 01:12:01 PM PDT 24
Finished Mar 19 01:31:21 PM PDT 24
Peak memory 336572 kb
Host smart-729d489a-d7c0-4032-af6c-29ec283b7eca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=206168143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.206168143 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.1472345265
Short name T604
Test name
Test status
Simulation time 48435586344 ps
CPU time 1011.85 seconds
Started Mar 19 01:11:57 PM PDT 24
Finished Mar 19 01:28:50 PM PDT 24
Peak memory 293748 kb
Host smart-9836d439-0663-4f30-b1dd-fcf6e46a46b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1472345265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.1472345265 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.3099334987
Short name T425
Test name
Test status
Simulation time 105144520223 ps
CPU time 4240.55 seconds
Started Mar 19 01:11:56 PM PDT 24
Finished Mar 19 02:22:38 PM PDT 24
Peak memory 642576 kb
Host smart-2ac51033-7f3c-4cd6-a37e-20f61db3c0b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3099334987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.3099334987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.3003698434
Short name T324
Test name
Test status
Simulation time 910268049383 ps
CPU time 4170.46 seconds
Started Mar 19 01:11:57 PM PDT 24
Finished Mar 19 02:21:29 PM PDT 24
Peak memory 568160 kb
Host smart-4841a105-30d9-4ed5-9fe6-20b4c457049d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3003698434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.3003698434 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.804287747
Short name T679
Test name
Test status
Simulation time 13323732 ps
CPU time 0.78 seconds
Started Mar 19 01:12:15 PM PDT 24
Finished Mar 19 01:12:16 PM PDT 24
Peak memory 205380 kb
Host smart-d850c718-a379-4482-85a8-7acdb2a719da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804287747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.804287747 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.1869739045
Short name T818
Test name
Test status
Simulation time 4594215122 ps
CPU time 43.83 seconds
Started Mar 19 01:12:14 PM PDT 24
Finished Mar 19 01:12:57 PM PDT 24
Peak memory 223416 kb
Host smart-c9a49ed3-0a99-47aa-85d0-e722fa230638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869739045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.1869739045 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.4008387803
Short name T44
Test name
Test status
Simulation time 1596912279 ps
CPU time 121.72 seconds
Started Mar 19 01:12:07 PM PDT 24
Finished Mar 19 01:14:09 PM PDT 24
Peak memory 220664 kb
Host smart-808ede45-98c1-4c36-be7a-b78d4d05ed36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008387803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.4008387803 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.3027541543
Short name T111
Test name
Test status
Simulation time 47285522458 ps
CPU time 155.16 seconds
Started Mar 19 01:12:11 PM PDT 24
Finished Mar 19 01:14:46 PM PDT 24
Peak memory 233480 kb
Host smart-668ae12b-1cab-42b0-8eee-3a5caa498d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027541543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.3027541543 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.2913367325
Short name T726
Test name
Test status
Simulation time 6285608453 ps
CPU time 23.47 seconds
Started Mar 19 01:12:13 PM PDT 24
Finished Mar 19 01:12:37 PM PDT 24
Peak memory 232380 kb
Host smart-3559d3b0-e48d-41fd-9f9f-7d91978ec635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913367325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.2913367325 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.2157478934
Short name T572
Test name
Test status
Simulation time 324636567 ps
CPU time 2.09 seconds
Started Mar 19 01:12:14 PM PDT 24
Finished Mar 19 01:12:17 PM PDT 24
Peak memory 207200 kb
Host smart-31ab082d-3e58-406d-ba76-2cf32bfc4d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157478934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.2157478934 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.413362489
Short name T226
Test name
Test status
Simulation time 83892522680 ps
CPU time 1861.12 seconds
Started Mar 19 01:12:06 PM PDT 24
Finished Mar 19 01:43:08 PM PDT 24
Peak memory 372868 kb
Host smart-9972685e-810e-4973-a3f6-dc6cc54db6bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413362489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_an
d_output.413362489 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.3148780195
Short name T191
Test name
Test status
Simulation time 1265605633 ps
CPU time 17.3 seconds
Started Mar 19 01:12:05 PM PDT 24
Finished Mar 19 01:12:22 PM PDT 24
Peak memory 224100 kb
Host smart-b8cd6ae0-da80-4c57-ae4a-88192af960a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148780195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.3148780195 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.217273152
Short name T821
Test name
Test status
Simulation time 1257579749 ps
CPU time 20.3 seconds
Started Mar 19 01:12:12 PM PDT 24
Finished Mar 19 01:12:33 PM PDT 24
Peak memory 218560 kb
Host smart-5bfec5ed-49e5-4e05-9cb9-7b7014240a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217273152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.217273152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.2009225843
Short name T518
Test name
Test status
Simulation time 685726050 ps
CPU time 4.57 seconds
Started Mar 19 01:12:15 PM PDT 24
Finished Mar 19 01:12:19 PM PDT 24
Peak memory 215984 kb
Host smart-fdcbfbbe-d147-4615-baab-0aedd74767b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2009225843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2009225843 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.4040115274
Short name T209
Test name
Test status
Simulation time 643330929 ps
CPU time 5.24 seconds
Started Mar 19 01:12:07 PM PDT 24
Finished Mar 19 01:12:12 PM PDT 24
Peak memory 215936 kb
Host smart-d71fd613-ddf3-499e-a09c-7db6b4760221
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040115274 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.4040115274 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.2656128252
Short name T75
Test name
Test status
Simulation time 76363438 ps
CPU time 4.34 seconds
Started Mar 19 01:12:06 PM PDT 24
Finished Mar 19 01:12:11 PM PDT 24
Peak memory 209164 kb
Host smart-b3f332cb-ef8e-419d-8e0f-978ea7ce2983
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656128252 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.kmac_test_vectors_kmac_xof.2656128252 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.351770561
Short name T871
Test name
Test status
Simulation time 198062158045 ps
CPU time 1977.34 seconds
Started Mar 19 01:12:06 PM PDT 24
Finished Mar 19 01:45:04 PM PDT 24
Peak memory 391968 kb
Host smart-efe9918b-1836-44a5-ad10-e1a69ea861ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=351770561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.351770561 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.1640054498
Short name T926
Test name
Test status
Simulation time 92049060381 ps
CPU time 1767.05 seconds
Started Mar 19 01:12:05 PM PDT 24
Finished Mar 19 01:41:33 PM PDT 24
Peak memory 369476 kb
Host smart-fd3bd838-d4eb-4404-9afa-56edcc8798ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1640054498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.1640054498 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.2503318390
Short name T601
Test name
Test status
Simulation time 27194896153 ps
CPU time 1166.34 seconds
Started Mar 19 01:12:03 PM PDT 24
Finished Mar 19 01:31:29 PM PDT 24
Peak memory 334168 kb
Host smart-055caf57-c2d9-43b1-93d1-411d434e56f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2503318390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.2503318390 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.1566498382
Short name T991
Test name
Test status
Simulation time 32789984807 ps
CPU time 874.8 seconds
Started Mar 19 01:12:07 PM PDT 24
Finished Mar 19 01:26:42 PM PDT 24
Peak memory 288056 kb
Host smart-8c6d8908-7f65-4ac2-9072-6fe147154a13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1566498382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.1566498382 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.4186999407
Short name T771
Test name
Test status
Simulation time 189187138839 ps
CPU time 5145.22 seconds
Started Mar 19 01:12:06 PM PDT 24
Finished Mar 19 02:37:52 PM PDT 24
Peak memory 652384 kb
Host smart-9601aebb-a67c-465c-8f05-893bf9e294e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4186999407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.4186999407 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.3165431005
Short name T934
Test name
Test status
Simulation time 145069254310 ps
CPU time 4179.71 seconds
Started Mar 19 01:12:06 PM PDT 24
Finished Mar 19 02:21:47 PM PDT 24
Peak memory 559828 kb
Host smart-a6180533-6870-4310-a250-a9867eaaff80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3165431005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.3165431005 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.1134364304
Short name T649
Test name
Test status
Simulation time 207626479 ps
CPU time 0.75 seconds
Started Mar 19 01:04:07 PM PDT 24
Finished Mar 19 01:04:08 PM PDT 24
Peak memory 205352 kb
Host smart-331fb01d-e16e-4caa-8600-9e9a7a084e25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134364304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1134364304 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.2701670548
Short name T184
Test name
Test status
Simulation time 53780085442 ps
CPU time 172.79 seconds
Started Mar 19 01:04:00 PM PDT 24
Finished Mar 19 01:06:53 PM PDT 24
Peak memory 237676 kb
Host smart-1f1ee2e3-6d21-4007-8f9e-e887e72d3060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701670548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.2701670548 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.3501399558
Short name T468
Test name
Test status
Simulation time 250899877 ps
CPU time 7.24 seconds
Started Mar 19 01:03:58 PM PDT 24
Finished Mar 19 01:04:06 PM PDT 24
Peak memory 224076 kb
Host smart-93c2691c-3491-4b7c-a6a1-0e07964ddbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501399558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.3501399558 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.22223460
Short name T45
Test name
Test status
Simulation time 6895163923 ps
CPU time 615.79 seconds
Started Mar 19 01:03:57 PM PDT 24
Finished Mar 19 01:14:14 PM PDT 24
Peak memory 231252 kb
Host smart-711a33fa-a0e0-4638-bdb6-da1c7d4090b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22223460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.22223460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.1275201719
Short name T883
Test name
Test status
Simulation time 2204360854 ps
CPU time 27.4 seconds
Started Mar 19 01:04:01 PM PDT 24
Finished Mar 19 01:04:28 PM PDT 24
Peak memory 225068 kb
Host smart-c48019ef-310d-4ca9-86a6-1b107205ba4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1275201719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1275201719 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.1468469650
Short name T792
Test name
Test status
Simulation time 1663491538 ps
CPU time 27.61 seconds
Started Mar 19 01:04:07 PM PDT 24
Finished Mar 19 01:04:36 PM PDT 24
Peak memory 220312 kb
Host smart-072cbe3c-9ae5-4316-8af7-42a2dddb7428
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1468469650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1468469650 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.2662174685
Short name T343
Test name
Test status
Simulation time 270069805 ps
CPU time 1.35 seconds
Started Mar 19 01:04:07 PM PDT 24
Finished Mar 19 01:04:09 PM PDT 24
Peak memory 215840 kb
Host smart-8604442f-e167-4932-977f-a90d71731861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662174685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2662174685 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.3527045841
Short name T370
Test name
Test status
Simulation time 8085830808 ps
CPU time 125.35 seconds
Started Mar 19 01:03:56 PM PDT 24
Finished Mar 19 01:06:02 PM PDT 24
Peak memory 231124 kb
Host smart-e2730d87-da2c-4645-9ff0-0a8217349547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527045841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.3527045841 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.3719389237
Short name T1040
Test name
Test status
Simulation time 40313864635 ps
CPU time 188.55 seconds
Started Mar 19 01:03:57 PM PDT 24
Finished Mar 19 01:07:06 PM PDT 24
Peak memory 253340 kb
Host smart-b47fabea-e27d-43db-80db-89c353d816f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719389237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.3719389237 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.335622174
Short name T62
Test name
Test status
Simulation time 1268901675 ps
CPU time 4.4 seconds
Started Mar 19 01:03:55 PM PDT 24
Finished Mar 19 01:04:01 PM PDT 24
Peak memory 207652 kb
Host smart-7b49b77d-f45c-4c4c-927f-c734167f6605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335622174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.335622174 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.1896638422
Short name T295
Test name
Test status
Simulation time 32550222 ps
CPU time 1.18 seconds
Started Mar 19 01:04:11 PM PDT 24
Finished Mar 19 01:04:12 PM PDT 24
Peak memory 215856 kb
Host smart-32e9f330-2d5e-4f06-a2d8-27964a317630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896638422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.1896638422 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.4290702372
Short name T1012
Test name
Test status
Simulation time 1688824378911 ps
CPU time 3013.89 seconds
Started Mar 19 01:03:56 PM PDT 24
Finished Mar 19 01:54:11 PM PDT 24
Peak memory 457676 kb
Host smart-6d69877d-01cc-461d-9c43-5667c3a8e904
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290702372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.4290702372 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.44205454
Short name T829
Test name
Test status
Simulation time 6402746618 ps
CPU time 153.71 seconds
Started Mar 19 01:03:56 PM PDT 24
Finished Mar 19 01:06:31 PM PDT 24
Peak memory 236548 kb
Host smart-faf1049b-5840-4825-b3d4-b93d4274fbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44205454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.44205454 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.1150964055
Short name T185
Test name
Test status
Simulation time 33245051785 ps
CPU time 219.54 seconds
Started Mar 19 01:04:01 PM PDT 24
Finished Mar 19 01:07:41 PM PDT 24
Peak memory 239500 kb
Host smart-14668ee8-bab0-450e-829e-6fb24ee75709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150964055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.1150964055 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.404049731
Short name T281
Test name
Test status
Simulation time 191756417 ps
CPU time 2.03 seconds
Started Mar 19 01:03:58 PM PDT 24
Finished Mar 19 01:04:00 PM PDT 24
Peak memory 216076 kb
Host smart-d3fbf194-f92a-4d75-9610-ab0bf4c26f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404049731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.404049731 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.945295767
Short name T28
Test name
Test status
Simulation time 52859901196 ps
CPU time 606.16 seconds
Started Mar 19 01:04:08 PM PDT 24
Finished Mar 19 01:14:16 PM PDT 24
Peak memory 288100 kb
Host smart-639546c9-13bc-4bf7-be9e-e6f38f6fb288
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=945295767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.945295767 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_stress_all_with_rand_reset.1972596647
Short name T122
Test name
Test status
Simulation time 13903696768 ps
CPU time 326.28 seconds
Started Mar 19 01:04:06 PM PDT 24
Finished Mar 19 01:09:33 PM PDT 24
Peak memory 257252 kb
Host smart-4357d2d3-2dc6-49f8-9a31-8e56ffca8090
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1972596647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.1972596647 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.3499571386
Short name T396
Test name
Test status
Simulation time 61788964 ps
CPU time 3.3 seconds
Started Mar 19 01:04:01 PM PDT 24
Finished Mar 19 01:04:04 PM PDT 24
Peak memory 215896 kb
Host smart-7ca64aae-dab0-4078-8be6-186b714be07f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499571386 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.kmac_test_vectors_kmac.3499571386 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.3798457755
Short name T967
Test name
Test status
Simulation time 235418711 ps
CPU time 4.64 seconds
Started Mar 19 01:03:57 PM PDT 24
Finished Mar 19 01:04:03 PM PDT 24
Peak memory 215880 kb
Host smart-8cb5f46f-c0a7-4b40-bc11-cdf7468b905b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798457755 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_test_vectors_kmac_xof.3798457755 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.691832106
Short name T384
Test name
Test status
Simulation time 37978907980 ps
CPU time 1509.21 seconds
Started Mar 19 01:03:53 PM PDT 24
Finished Mar 19 01:29:03 PM PDT 24
Peak memory 387908 kb
Host smart-691ff14e-57e8-4808-9b17-fc44750022ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=691832106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.691832106 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.1127307917
Short name T860
Test name
Test status
Simulation time 244219097293 ps
CPU time 1686.5 seconds
Started Mar 19 01:03:57 PM PDT 24
Finished Mar 19 01:32:04 PM PDT 24
Peak memory 373760 kb
Host smart-4ab407aa-010c-44b6-afab-b70bb7d79337
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1127307917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.1127307917 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.3944418423
Short name T1018
Test name
Test status
Simulation time 57358178359 ps
CPU time 1136.29 seconds
Started Mar 19 01:03:56 PM PDT 24
Finished Mar 19 01:22:53 PM PDT 24
Peak memory 338144 kb
Host smart-446e8f50-ef4a-4ed4-82dd-a7a2f1f0e850
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3944418423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.3944418423 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.283433759
Short name T15
Test name
Test status
Simulation time 9304201700 ps
CPU time 700.41 seconds
Started Mar 19 01:03:56 PM PDT 24
Finished Mar 19 01:15:37 PM PDT 24
Peak memory 290472 kb
Host smart-dedaae8d-a813-48d7-8812-8e3a75c07380
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=283433759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.283433759 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.3769694141
Short name T351
Test name
Test status
Simulation time 213863338837 ps
CPU time 4852.55 seconds
Started Mar 19 01:03:58 PM PDT 24
Finished Mar 19 02:24:51 PM PDT 24
Peak memory 646384 kb
Host smart-45887e32-319f-4aeb-9960-9fab493a8960
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3769694141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.3769694141 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.1233696530
Short name T293
Test name
Test status
Simulation time 664452129311 ps
CPU time 4161.65 seconds
Started Mar 19 01:03:56 PM PDT 24
Finished Mar 19 02:13:19 PM PDT 24
Peak memory 552208 kb
Host smart-5deeb1e2-f0ea-461f-ac0a-ce44b1e39f6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1233696530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.1233696530 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.3727627009
Short name T328
Test name
Test status
Simulation time 39326195 ps
CPU time 0.77 seconds
Started Mar 19 01:04:10 PM PDT 24
Finished Mar 19 01:04:11 PM PDT 24
Peak memory 205352 kb
Host smart-3815c788-28e9-44e0-b052-f5ad8d57ad77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727627009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.3727627009 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.3073626492
Short name T257
Test name
Test status
Simulation time 5981014096 ps
CPU time 141.03 seconds
Started Mar 19 01:04:10 PM PDT 24
Finished Mar 19 01:06:32 PM PDT 24
Peak memory 232692 kb
Host smart-9af60ffe-460d-4f8b-bbc8-3ce933457a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073626492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.3073626492 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.3029397865
Short name T221
Test name
Test status
Simulation time 813030456 ps
CPU time 10.27 seconds
Started Mar 19 01:04:10 PM PDT 24
Finished Mar 19 01:04:21 PM PDT 24
Peak memory 224144 kb
Host smart-1f8caf43-100b-4969-8852-051c25449b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029397865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.3029397865 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.2498936810
Short name T847
Test name
Test status
Simulation time 21831004528 ps
CPU time 64.96 seconds
Started Mar 19 01:04:09 PM PDT 24
Finished Mar 19 01:05:14 PM PDT 24
Peak memory 219724 kb
Host smart-ee37512f-e609-4740-8337-0d39b4de86be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498936810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.2498936810 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.3585946891
Short name T193
Test name
Test status
Simulation time 161734614 ps
CPU time 9.86 seconds
Started Mar 19 01:04:08 PM PDT 24
Finished Mar 19 01:04:19 PM PDT 24
Peak memory 223812 kb
Host smart-589e70a7-448e-4151-89f7-14f8bcabbe53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3585946891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.3585946891 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.1496073175
Short name T1013
Test name
Test status
Simulation time 22436973568 ps
CPU time 26.61 seconds
Started Mar 19 01:04:07 PM PDT 24
Finished Mar 19 01:04:34 PM PDT 24
Peak memory 219412 kb
Host smart-5fc29255-541a-4467-96e1-3147987a405b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1496073175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.1496073175 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.1950253405
Short name T112
Test name
Test status
Simulation time 1032845127 ps
CPU time 10.49 seconds
Started Mar 19 01:04:08 PM PDT 24
Finished Mar 19 01:04:20 PM PDT 24
Peak memory 216616 kb
Host smart-963156e9-6665-4184-87d4-fee364401b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950253405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.1950253405 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.2394674776
Short name T747
Test name
Test status
Simulation time 4967768685 ps
CPU time 128.67 seconds
Started Mar 19 01:04:09 PM PDT 24
Finished Mar 19 01:06:18 PM PDT 24
Peak memory 233788 kb
Host smart-0fa8d86a-e666-424e-9b52-1bf403872e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394674776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.2394674776 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.1728081192
Short name T381
Test name
Test status
Simulation time 13296600574 ps
CPU time 91.18 seconds
Started Mar 19 01:04:08 PM PDT 24
Finished Mar 19 01:05:39 PM PDT 24
Peak memory 240544 kb
Host smart-3ab3f2a7-87f1-4896-8947-289e5b1d55d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728081192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.1728081192 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.3005287167
Short name T723
Test name
Test status
Simulation time 1213637941 ps
CPU time 3.35 seconds
Started Mar 19 01:04:07 PM PDT 24
Finished Mar 19 01:04:11 PM PDT 24
Peak memory 207380 kb
Host smart-4ec9e5be-8955-4977-bb77-4594bfa8eef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005287167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.3005287167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.487195716
Short name T271
Test name
Test status
Simulation time 4792822862 ps
CPU time 94.54 seconds
Started Mar 19 01:04:08 PM PDT 24
Finished Mar 19 01:05:43 PM PDT 24
Peak memory 232428 kb
Host smart-be274baa-f087-4eaa-b59b-4a008c512ccb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487195716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and
_output.487195716 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.2405296857
Short name T86
Test name
Test status
Simulation time 499062333 ps
CPU time 29.35 seconds
Started Mar 19 01:04:07 PM PDT 24
Finished Mar 19 01:04:37 PM PDT 24
Peak memory 224308 kb
Host smart-e2a9f4bb-a6e3-409b-a3e9-bfa9738a665c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405296857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.2405296857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.2985122911
Short name T470
Test name
Test status
Simulation time 6177733645 ps
CPU time 50.73 seconds
Started Mar 19 01:04:12 PM PDT 24
Finished Mar 19 01:05:03 PM PDT 24
Peak memory 224120 kb
Host smart-d0f0aacd-35a5-44d3-a7a8-914687271e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985122911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.2985122911 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.4143925426
Short name T912
Test name
Test status
Simulation time 510665257 ps
CPU time 27.5 seconds
Started Mar 19 01:04:09 PM PDT 24
Finished Mar 19 01:04:37 PM PDT 24
Peak memory 221840 kb
Host smart-431a5a32-1e02-489c-995c-18fa8fef7da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143925426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.4143925426 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.2528236190
Short name T736
Test name
Test status
Simulation time 9366202159 ps
CPU time 97.89 seconds
Started Mar 19 01:04:07 PM PDT 24
Finished Mar 19 01:05:45 PM PDT 24
Peak memory 251628 kb
Host smart-6f813350-1fdd-4971-916b-065530180be6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2528236190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.2528236190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.1025832297
Short name T273
Test name
Test status
Simulation time 183477140 ps
CPU time 4.67 seconds
Started Mar 19 01:04:06 PM PDT 24
Finished Mar 19 01:04:11 PM PDT 24
Peak memory 215916 kb
Host smart-58bbe3ab-acf0-45d6-bede-5bab190ee4c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025832297 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.1025832297 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.2172483293
Short name T596
Test name
Test status
Simulation time 1893530852 ps
CPU time 4.94 seconds
Started Mar 19 01:04:06 PM PDT 24
Finished Mar 19 01:04:12 PM PDT 24
Peak memory 215964 kb
Host smart-711fe4bb-d978-432c-8b2f-3f264a978e8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172483293 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_test_vectors_kmac_xof.2172483293 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.3791920981
Short name T933
Test name
Test status
Simulation time 65744128649 ps
CPU time 1760.66 seconds
Started Mar 19 01:04:14 PM PDT 24
Finished Mar 19 01:33:35 PM PDT 24
Peak memory 397152 kb
Host smart-86a7e567-df31-4c2f-a58d-ddc48a6dad88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3791920981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.3791920981 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.2835477962
Short name T711
Test name
Test status
Simulation time 72708451756 ps
CPU time 1536.49 seconds
Started Mar 19 01:04:08 PM PDT 24
Finished Mar 19 01:29:46 PM PDT 24
Peak memory 389824 kb
Host smart-7e27ace7-09ef-45e1-a183-2259eed70a16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2835477962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.2835477962 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.4219391071
Short name T458
Test name
Test status
Simulation time 48875285401 ps
CPU time 1320.16 seconds
Started Mar 19 01:04:07 PM PDT 24
Finished Mar 19 01:26:08 PM PDT 24
Peak memory 335252 kb
Host smart-891653c5-6a41-406e-8d3d-75e704dcfec9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4219391071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.4219391071 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.1132476796
Short name T1053
Test name
Test status
Simulation time 44569764979 ps
CPU time 759.09 seconds
Started Mar 19 01:04:06 PM PDT 24
Finished Mar 19 01:16:46 PM PDT 24
Peak memory 292364 kb
Host smart-e6eda5c6-ea80-4a41-8f09-081ecbf8c4d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1132476796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.1132476796 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.212801352
Short name T461
Test name
Test status
Simulation time 266877233460 ps
CPU time 5276.43 seconds
Started Mar 19 01:04:04 PM PDT 24
Finished Mar 19 02:32:01 PM PDT 24
Peak memory 649136 kb
Host smart-44914c3c-a4af-4d06-8af0-504dfd6b6f10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=212801352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.212801352 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.1561008497
Short name T813
Test name
Test status
Simulation time 153076288364 ps
CPU time 3983.25 seconds
Started Mar 19 01:04:14 PM PDT 24
Finished Mar 19 02:10:38 PM PDT 24
Peak memory 573344 kb
Host smart-55498454-094f-41a8-9e84-ee547393160d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1561008497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.1561008497 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.3273726129
Short name T1056
Test name
Test status
Simulation time 88416984 ps
CPU time 0.83 seconds
Started Mar 19 01:04:17 PM PDT 24
Finished Mar 19 01:04:18 PM PDT 24
Peak memory 205400 kb
Host smart-b5a3ec5a-6350-48cc-b5db-24dd182ab7c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273726129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3273726129 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.1454633920
Short name T872
Test name
Test status
Simulation time 474508509 ps
CPU time 18.12 seconds
Started Mar 19 01:04:08 PM PDT 24
Finished Mar 19 01:04:27 PM PDT 24
Peak memory 217880 kb
Host smart-19b588ce-f058-4adc-ac00-89d25b19e5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454633920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.1454633920 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.2611696328
Short name T557
Test name
Test status
Simulation time 71927594345 ps
CPU time 259.96 seconds
Started Mar 19 01:04:06 PM PDT 24
Finished Mar 19 01:08:27 PM PDT 24
Peak memory 246188 kb
Host smart-cc9179ba-fa33-4b5c-a21b-af1042e85a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611696328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.2611696328 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.3730250528
Short name T506
Test name
Test status
Simulation time 31469133833 ps
CPU time 778.53 seconds
Started Mar 19 01:04:09 PM PDT 24
Finished Mar 19 01:17:08 PM PDT 24
Peak memory 231812 kb
Host smart-fdce5d6b-6c4c-4baf-8ecd-03c0d2afb6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730250528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3730250528 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.1139943782
Short name T585
Test name
Test status
Simulation time 463254463 ps
CPU time 17.66 seconds
Started Mar 19 01:04:19 PM PDT 24
Finished Mar 19 01:04:37 PM PDT 24
Peak memory 223892 kb
Host smart-66dc79cc-21c1-4f8e-8d5f-9e7b2d3dc04a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1139943782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.1139943782 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.2915700991
Short name T584
Test name
Test status
Simulation time 1603914659 ps
CPU time 22.01 seconds
Started Mar 19 01:04:17 PM PDT 24
Finished Mar 19 01:04:39 PM PDT 24
Peak memory 223904 kb
Host smart-fd9bcb9e-4c3d-45d1-b304-b2ff82310026
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2915700991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.2915700991 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.1814882290
Short name T268
Test name
Test status
Simulation time 828787949 ps
CPU time 7.93 seconds
Started Mar 19 01:04:18 PM PDT 24
Finished Mar 19 01:04:26 PM PDT 24
Peak memory 217012 kb
Host smart-44925a37-59d8-4194-9fe0-c1a4515382bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814882290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.1814882290 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.2358500179
Short name T636
Test name
Test status
Simulation time 13176752136 ps
CPU time 198.28 seconds
Started Mar 19 01:04:17 PM PDT 24
Finished Mar 19 01:07:35 PM PDT 24
Peak memory 239416 kb
Host smart-8878c758-dce2-40c9-9456-ebef824a34fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358500179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.2358500179 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.1442850025
Short name T489
Test name
Test status
Simulation time 47535760499 ps
CPU time 320.66 seconds
Started Mar 19 01:04:18 PM PDT 24
Finished Mar 19 01:09:39 PM PDT 24
Peak memory 257300 kb
Host smart-73b5d034-46a0-4518-8c0a-e0a6800fcf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442850025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.1442850025 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.754743854
Short name T946
Test name
Test status
Simulation time 7594087645 ps
CPU time 6.47 seconds
Started Mar 19 01:04:20 PM PDT 24
Finished Mar 19 01:04:27 PM PDT 24
Peak memory 207676 kb
Host smart-afe7da1a-8bec-44fa-a6b8-717ad85a9a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754743854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.754743854 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.3187006981
Short name T579
Test name
Test status
Simulation time 37155850 ps
CPU time 1.21 seconds
Started Mar 19 01:04:20 PM PDT 24
Finished Mar 19 01:04:22 PM PDT 24
Peak memory 215852 kb
Host smart-03edcbd5-ac80-4cf2-8d7e-9b9b86ca919a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187006981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.3187006981 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.2043063858
Short name T549
Test name
Test status
Simulation time 440533865638 ps
CPU time 1774.26 seconds
Started Mar 19 01:04:07 PM PDT 24
Finished Mar 19 01:33:42 PM PDT 24
Peak memory 371788 kb
Host smart-a6b8a04b-5fab-4e20-8c0f-1e1dca084b0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043063858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.2043063858 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.1783281563
Short name T637
Test name
Test status
Simulation time 13532151946 ps
CPU time 123.46 seconds
Started Mar 19 01:04:19 PM PDT 24
Finished Mar 19 01:06:22 PM PDT 24
Peak memory 233620 kb
Host smart-2e8b152b-6d0b-4ae7-97a4-21190939b373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783281563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.1783281563 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.4266483781
Short name T274
Test name
Test status
Simulation time 12711227680 ps
CPU time 236.6 seconds
Started Mar 19 01:04:08 PM PDT 24
Finished Mar 19 01:08:05 PM PDT 24
Peak memory 243000 kb
Host smart-5101b9c8-8a13-4796-9330-febaeb58aee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266483781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.4266483781 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.185129233
Short name T678
Test name
Test status
Simulation time 955324929 ps
CPU time 11.51 seconds
Started Mar 19 01:04:05 PM PDT 24
Finished Mar 19 01:04:16 PM PDT 24
Peak memory 217064 kb
Host smart-b2369a76-b773-4dcd-842e-b1077f09dfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185129233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.185129233 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.2121616486
Short name T365
Test name
Test status
Simulation time 37373206279 ps
CPU time 525.72 seconds
Started Mar 19 01:04:19 PM PDT 24
Finished Mar 19 01:13:05 PM PDT 24
Peak memory 288564 kb
Host smart-44a30219-1986-44f7-8795-622df6944ca3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2121616486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2121616486 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.3322380750
Short name T473
Test name
Test status
Simulation time 81526610 ps
CPU time 4.11 seconds
Started Mar 19 01:04:08 PM PDT 24
Finished Mar 19 01:04:13 PM PDT 24
Peak memory 215956 kb
Host smart-d0c61fc7-ffa5-453b-82a8-4492bb45b78f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322380750 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.kmac_test_vectors_kmac.3322380750 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.1659341401
Short name T332
Test name
Test status
Simulation time 893572352 ps
CPU time 4.54 seconds
Started Mar 19 01:04:05 PM PDT 24
Finished Mar 19 01:04:10 PM PDT 24
Peak memory 215952 kb
Host smart-55f4efa3-f820-48cb-af6d-c51306bc6843
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659341401 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.1659341401 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.1791422745
Short name T485
Test name
Test status
Simulation time 496616850809 ps
CPU time 1892.75 seconds
Started Mar 19 01:04:08 PM PDT 24
Finished Mar 19 01:35:41 PM PDT 24
Peak memory 390328 kb
Host smart-ed11a946-b8e9-48b3-a745-f99a44edfc24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1791422745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.1791422745 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.1171142827
Short name T619
Test name
Test status
Simulation time 68327489090 ps
CPU time 1771.92 seconds
Started Mar 19 01:04:08 PM PDT 24
Finished Mar 19 01:33:40 PM PDT 24
Peak memory 392004 kb
Host smart-5eaff3fb-fe8b-4c5e-988f-23b6c3794c05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1171142827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.1171142827 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.2393614546
Short name T304
Test name
Test status
Simulation time 155267876300 ps
CPU time 1271.22 seconds
Started Mar 19 01:04:06 PM PDT 24
Finished Mar 19 01:25:18 PM PDT 24
Peak memory 326368 kb
Host smart-91e80069-f419-42db-abc5-de7134e1e6a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2393614546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.2393614546 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.4164317716
Short name T476
Test name
Test status
Simulation time 9711193259 ps
CPU time 781.67 seconds
Started Mar 19 01:04:06 PM PDT 24
Finished Mar 19 01:17:08 PM PDT 24
Peak memory 296724 kb
Host smart-36e37250-a407-445a-b066-8d159fe622bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4164317716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.4164317716 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.282201637
Short name T313
Test name
Test status
Simulation time 231473140788 ps
CPU time 4724.98 seconds
Started Mar 19 01:04:08 PM PDT 24
Finished Mar 19 02:22:54 PM PDT 24
Peak memory 637664 kb
Host smart-3a353c81-b1fa-4039-951b-752b75334972
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=282201637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.282201637 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.2146911116
Short name T824
Test name
Test status
Simulation time 172821449735 ps
CPU time 3466.52 seconds
Started Mar 19 01:04:08 PM PDT 24
Finished Mar 19 02:01:56 PM PDT 24
Peak memory 560180 kb
Host smart-d70e7b02-0651-46bc-9506-6ec1a2cb854b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2146911116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.2146911116 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.2762781031
Short name T310
Test name
Test status
Simulation time 17344271 ps
CPU time 0.82 seconds
Started Mar 19 01:04:19 PM PDT 24
Finished Mar 19 01:04:20 PM PDT 24
Peak memory 205396 kb
Host smart-87e85e43-2f20-464c-af30-929ba81eacbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762781031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.2762781031 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.2154608986
Short name T778
Test name
Test status
Simulation time 4005384091 ps
CPU time 185.01 seconds
Started Mar 19 01:04:17 PM PDT 24
Finished Mar 19 01:07:22 PM PDT 24
Peak memory 241292 kb
Host smart-9d3cfe02-db02-497e-aff4-363bfe6343cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154608986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.2154608986 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.4258822583
Short name T698
Test name
Test status
Simulation time 5407973181 ps
CPU time 269.09 seconds
Started Mar 19 01:04:19 PM PDT 24
Finished Mar 19 01:08:48 PM PDT 24
Peak memory 246384 kb
Host smart-446d9808-4296-410c-9103-19a5be2dee76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258822583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.4258822583 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.2325785243
Short name T47
Test name
Test status
Simulation time 16735050291 ps
CPU time 669.07 seconds
Started Mar 19 01:04:19 PM PDT 24
Finished Mar 19 01:15:28 PM PDT 24
Peak memory 233212 kb
Host smart-5fb0804b-e9c5-4b4a-aa01-bffe20ba6a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325785243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.2325785243 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.3799811273
Short name T864
Test name
Test status
Simulation time 370301416 ps
CPU time 9.41 seconds
Started Mar 19 01:04:19 PM PDT 24
Finished Mar 19 01:04:28 PM PDT 24
Peak memory 219348 kb
Host smart-f68d5e62-9b8b-4f5a-989f-b54e32605db5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3799811273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.3799811273 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.3170649230
Short name T278
Test name
Test status
Simulation time 533537025 ps
CPU time 29.71 seconds
Started Mar 19 01:04:18 PM PDT 24
Finished Mar 19 01:04:48 PM PDT 24
Peak memory 223764 kb
Host smart-79b39ac8-02c0-4d35-b6f4-e34d55383aab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3170649230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.3170649230 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.2621709051
Short name T318
Test name
Test status
Simulation time 1536521940 ps
CPU time 34.94 seconds
Started Mar 19 01:04:18 PM PDT 24
Finished Mar 19 01:04:53 PM PDT 24
Peak memory 224020 kb
Host smart-766f0d75-85b0-401b-b418-f6aeeaec2b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621709051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.2621709051 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.2624453078
Short name T443
Test name
Test status
Simulation time 70195579036 ps
CPU time 257.62 seconds
Started Mar 19 01:04:23 PM PDT 24
Finished Mar 19 01:08:40 PM PDT 24
Peak memory 252632 kb
Host smart-15a70378-d7cf-41d4-bd5e-08170b3f9658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624453078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.2624453078 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.1250539386
Short name T21
Test name
Test status
Simulation time 974696400 ps
CPU time 5 seconds
Started Mar 19 01:04:25 PM PDT 24
Finished Mar 19 01:04:30 PM PDT 24
Peak memory 207580 kb
Host smart-00584a7a-3976-4210-8b2d-ad9d6b710fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250539386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.1250539386 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.2767621714
Short name T542
Test name
Test status
Simulation time 33786072 ps
CPU time 1.13 seconds
Started Mar 19 01:04:18 PM PDT 24
Finished Mar 19 01:04:19 PM PDT 24
Peak memory 215828 kb
Host smart-2f3571d6-dc38-45ea-b689-b739c358cf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767621714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.2767621714 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.949717081
Short name T1039
Test name
Test status
Simulation time 173970365750 ps
CPU time 1082.13 seconds
Started Mar 19 01:04:16 PM PDT 24
Finished Mar 19 01:22:19 PM PDT 24
Peak memory 311264 kb
Host smart-d7c022a3-0813-44cd-ac13-f728fde3862c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949717081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and
_output.949717081 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.2418171207
Short name T626
Test name
Test status
Simulation time 5319273310 ps
CPU time 270.95 seconds
Started Mar 19 01:04:18 PM PDT 24
Finished Mar 19 01:08:49 PM PDT 24
Peak memory 248004 kb
Host smart-3ab77d7b-9f27-448c-932f-ccc3753881a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418171207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.2418171207 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.1735008415
Short name T880
Test name
Test status
Simulation time 5599619286 ps
CPU time 216.01 seconds
Started Mar 19 01:04:19 PM PDT 24
Finished Mar 19 01:07:55 PM PDT 24
Peak memory 239848 kb
Host smart-06701d25-3c49-434c-a91c-486193c36c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735008415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.1735008415 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.89166484
Short name T418
Test name
Test status
Simulation time 800215823 ps
CPU time 15.9 seconds
Started Mar 19 01:04:21 PM PDT 24
Finished Mar 19 01:04:37 PM PDT 24
Peak memory 224088 kb
Host smart-4d1db4ce-fc85-41ce-b022-03935cd10ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89166484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.89166484 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.3726903393
Short name T998
Test name
Test status
Simulation time 14126738087 ps
CPU time 273.67 seconds
Started Mar 19 01:04:20 PM PDT 24
Finished Mar 19 01:08:54 PM PDT 24
Peak memory 272548 kb
Host smart-d8635736-f5ed-4da5-834c-5785180b0e2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3726903393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.3726903393 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.114957453
Short name T252
Test name
Test status
Simulation time 213185585 ps
CPU time 4.62 seconds
Started Mar 19 01:04:17 PM PDT 24
Finished Mar 19 01:04:22 PM PDT 24
Peak memory 215920 kb
Host smart-12ee37d3-e752-422b-813e-11cbba0e1687
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114957453 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.kmac_test_vectors_kmac.114957453 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.4124278417
Short name T1043
Test name
Test status
Simulation time 1181669268 ps
CPU time 4.47 seconds
Started Mar 19 01:04:18 PM PDT 24
Finished Mar 19 01:04:23 PM PDT 24
Peak memory 215908 kb
Host smart-37ea887c-1ef3-4d9b-acb5-413e69045985
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124278417 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.4124278417 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.2293978041
Short name T156
Test name
Test status
Simulation time 68545066422 ps
CPU time 2033.72 seconds
Started Mar 19 01:04:18 PM PDT 24
Finished Mar 19 01:38:12 PM PDT 24
Peak memory 398216 kb
Host smart-2e376023-edc9-4964-a1a4-62661c721a0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2293978041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.2293978041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.1319367746
Short name T989
Test name
Test status
Simulation time 62906885532 ps
CPU time 1680.57 seconds
Started Mar 19 01:04:17 PM PDT 24
Finished Mar 19 01:32:18 PM PDT 24
Peak memory 373696 kb
Host smart-9ded4cbc-9ec1-41df-b314-fe9ad9a73ab8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1319367746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.1319367746 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.3979736832
Short name T405
Test name
Test status
Simulation time 199497630816 ps
CPU time 1151.48 seconds
Started Mar 19 01:04:18 PM PDT 24
Finished Mar 19 01:23:30 PM PDT 24
Peak memory 342324 kb
Host smart-7d8d70ab-dfd9-4ae7-b9b3-ab8500d3645f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3979736832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.3979736832 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.461519180
Short name T254
Test name
Test status
Simulation time 9635407543 ps
CPU time 792.31 seconds
Started Mar 19 01:04:25 PM PDT 24
Finished Mar 19 01:17:37 PM PDT 24
Peak memory 295476 kb
Host smart-6051ded1-dd5c-4d1f-93c5-ab171548f404
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=461519180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.461519180 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.1871445275
Short name T951
Test name
Test status
Simulation time 265356733387 ps
CPU time 4317.49 seconds
Started Mar 19 01:04:17 PM PDT 24
Finished Mar 19 02:16:15 PM PDT 24
Peak memory 641156 kb
Host smart-4fc45b97-e478-4284-b562-ad22dcc4d9d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1871445275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.1871445275 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.3853322807
Short name T621
Test name
Test status
Simulation time 257556659404 ps
CPU time 3480.97 seconds
Started Mar 19 01:04:20 PM PDT 24
Finished Mar 19 02:02:22 PM PDT 24
Peak memory 572644 kb
Host smart-9b56ddfb-4a38-4140-85e3-b3bb8e556a5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3853322807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.3853322807 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.2479707804
Short name T724
Test name
Test status
Simulation time 17826178 ps
CPU time 0.79 seconds
Started Mar 19 01:04:32 PM PDT 24
Finished Mar 19 01:04:32 PM PDT 24
Peak memory 205672 kb
Host smart-59eb5c51-2b91-40a7-8ee8-871e67780d25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479707804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.2479707804 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.1559556796
Short name T363
Test name
Test status
Simulation time 15363924590 ps
CPU time 99.26 seconds
Started Mar 19 01:04:24 PM PDT 24
Finished Mar 19 01:06:03 PM PDT 24
Peak memory 229056 kb
Host smart-947fa870-36f2-4ba6-992f-475ad34c543e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559556796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.1559556796 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.1219307248
Short name T970
Test name
Test status
Simulation time 4539761874 ps
CPU time 36.87 seconds
Started Mar 19 01:04:20 PM PDT 24
Finished Mar 19 01:04:57 PM PDT 24
Peak memory 224100 kb
Host smart-3e62405f-ed9d-490c-8e3c-482d083f0a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219307248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.1219307248 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.1496829774
Short name T14
Test name
Test status
Simulation time 4614816249 ps
CPU time 69.36 seconds
Started Mar 19 01:04:19 PM PDT 24
Finished Mar 19 01:05:28 PM PDT 24
Peak memory 224164 kb
Host smart-9273b33c-bcd7-444d-8316-f012eb3d8269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496829774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.1496829774 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.2020700599
Short name T590
Test name
Test status
Simulation time 1958016556 ps
CPU time 38.8 seconds
Started Mar 19 01:04:27 PM PDT 24
Finished Mar 19 01:05:06 PM PDT 24
Peak memory 238160 kb
Host smart-672d4fd5-fcac-4d25-8995-65e58bc9b87b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2020700599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.2020700599 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.1121146647
Short name T764
Test name
Test status
Simulation time 1374299405 ps
CPU time 24.62 seconds
Started Mar 19 01:04:26 PM PDT 24
Finished Mar 19 01:04:51 PM PDT 24
Peak memory 223772 kb
Host smart-3cf099a6-e821-4a7f-8af6-24503ba3bf17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1121146647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.1121146647 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.4258903999
Short name T755
Test name
Test status
Simulation time 4400938240 ps
CPU time 47.49 seconds
Started Mar 19 01:04:33 PM PDT 24
Finished Mar 19 01:05:21 PM PDT 24
Peak memory 223616 kb
Host smart-232eeaf9-12ed-41b3-9127-5c52d1b505f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258903999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.4258903999 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.3826221804
Short name T420
Test name
Test status
Simulation time 6682413033 ps
CPU time 27.11 seconds
Started Mar 19 01:04:28 PM PDT 24
Finished Mar 19 01:04:55 PM PDT 24
Peak memory 224176 kb
Host smart-da017a3b-afbb-47e7-b466-2a92ea2f28d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826221804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.3826221804 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.1700446408
Short name T1078
Test name
Test status
Simulation time 520120008 ps
CPU time 31.79 seconds
Started Mar 19 01:04:27 PM PDT 24
Finished Mar 19 01:04:59 PM PDT 24
Peak memory 238472 kb
Host smart-8f4a4af7-8073-48b2-b0ac-f166c78f51c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700446408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.1700446408 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.3658379095
Short name T861
Test name
Test status
Simulation time 2519788688 ps
CPU time 4.18 seconds
Started Mar 19 01:04:28 PM PDT 24
Finished Mar 19 01:04:33 PM PDT 24
Peak memory 207620 kb
Host smart-e178135e-b039-4478-ab48-c819748ea2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658379095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.3658379095 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.488704953
Short name T389
Test name
Test status
Simulation time 190951426 ps
CPU time 7.75 seconds
Started Mar 19 01:04:32 PM PDT 24
Finished Mar 19 01:04:40 PM PDT 24
Peak memory 224416 kb
Host smart-6a96c789-9d1f-41df-ad6c-698aa454586d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488704953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.488704953 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.1987777034
Short name T776
Test name
Test status
Simulation time 8958058394 ps
CPU time 814.69 seconds
Started Mar 19 01:04:17 PM PDT 24
Finished Mar 19 01:17:52 PM PDT 24
Peak memory 304316 kb
Host smart-38fa208c-cdee-494f-895d-3e3f29e1cdb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987777034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.1987777034 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.3226576134
Short name T1076
Test name
Test status
Simulation time 6086280927 ps
CPU time 195.34 seconds
Started Mar 19 01:04:27 PM PDT 24
Finished Mar 19 01:07:43 PM PDT 24
Peak memory 242960 kb
Host smart-8603625c-0807-4f03-b6ea-44aaf2f891c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226576134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.3226576134 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.628323649
Short name T400
Test name
Test status
Simulation time 122467739973 ps
CPU time 357.2 seconds
Started Mar 19 01:04:19 PM PDT 24
Finished Mar 19 01:10:16 PM PDT 24
Peak memory 246520 kb
Host smart-e6d57cdd-163b-4ddc-b985-ff4a993e1b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628323649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.628323649 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.35086956
Short name T220
Test name
Test status
Simulation time 134262941 ps
CPU time 6.53 seconds
Started Mar 19 01:04:28 PM PDT 24
Finished Mar 19 01:04:35 PM PDT 24
Peak memory 217176 kb
Host smart-d6552d5a-0b67-4d57-bc43-8c5bb7b81e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35086956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.35086956 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.3545541461
Short name T467
Test name
Test status
Simulation time 3438480388 ps
CPU time 232.37 seconds
Started Mar 19 01:04:26 PM PDT 24
Finished Mar 19 01:08:19 PM PDT 24
Peak memory 273624 kb
Host smart-d9dbec4f-fda1-447d-88a7-396dc8249f01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3545541461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.3545541461 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.1701860934
Short name T78
Test name
Test status
Simulation time 909865291 ps
CPU time 4.83 seconds
Started Mar 19 01:04:22 PM PDT 24
Finished Mar 19 01:04:26 PM PDT 24
Peak memory 216024 kb
Host smart-682bfc5b-f04d-460e-99a2-7d5ac0d66a56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701860934 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.1701860934 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.2010100587
Short name T1054
Test name
Test status
Simulation time 72929109 ps
CPU time 3.95 seconds
Started Mar 19 01:04:17 PM PDT 24
Finished Mar 19 01:04:21 PM PDT 24
Peak memory 215928 kb
Host smart-0b66d3d8-d2bb-4898-868f-f500dfe95661
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010100587 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.kmac_test_vectors_kmac_xof.2010100587 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.727315587
Short name T642
Test name
Test status
Simulation time 333806125069 ps
CPU time 1861.44 seconds
Started Mar 19 01:04:18 PM PDT 24
Finished Mar 19 01:35:19 PM PDT 24
Peak memory 388240 kb
Host smart-7846a1a3-164b-4d38-a69c-e3304a3c983b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=727315587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.727315587 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.21294797
Short name T562
Test name
Test status
Simulation time 259031911221 ps
CPU time 1789.73 seconds
Started Mar 19 01:04:19 PM PDT 24
Finished Mar 19 01:34:09 PM PDT 24
Peak memory 387152 kb
Host smart-7f184e0c-744c-4672-bbbc-c3112c679898
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=21294797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.21294797 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.1097849638
Short name T409
Test name
Test status
Simulation time 54790342300 ps
CPU time 1046.57 seconds
Started Mar 19 01:04:17 PM PDT 24
Finished Mar 19 01:21:44 PM PDT 24
Peak memory 335836 kb
Host smart-1607377d-440b-47cc-8741-829382af4670
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1097849638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.1097849638 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.4156535709
Short name T702
Test name
Test status
Simulation time 135203871464 ps
CPU time 970.23 seconds
Started Mar 19 01:04:20 PM PDT 24
Finished Mar 19 01:20:31 PM PDT 24
Peak memory 294060 kb
Host smart-eb31a62a-5780-4062-afe0-d22fcc6c476f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4156535709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.4156535709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.768100693
Short name T838
Test name
Test status
Simulation time 106693605688 ps
CPU time 4164.85 seconds
Started Mar 19 01:04:29 PM PDT 24
Finished Mar 19 02:13:55 PM PDT 24
Peak memory 658212 kb
Host smart-0850e400-b998-452d-8ba3-b94ea0032113
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=768100693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.768100693 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.492444848
Short name T1051
Test name
Test status
Simulation time 287656240787 ps
CPU time 3449.67 seconds
Started Mar 19 01:04:19 PM PDT 24
Finished Mar 19 02:01:49 PM PDT 24
Peak memory 558296 kb
Host smart-b334607f-0335-47b8-aa48-5e66c2ba95d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=492444848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.492444848 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%