Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100785228	1			T2	36732		T4	455		T5	3
all_values[1]	100785228	1			T2	36732		T4	455		T5	3
all_values[2]	100785228	1			T2	36732		T4	455		T5	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

451911

1

T2

3855

T5

3

T14

32

auto[1]

301903773

1

T2

106341

T4

1365

T5

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300826548

1

T2

108774

T4

1350

T5

9

auto[1]

1529136

1

T2

1422

T4

15

T14

1746

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	152271	1			T2	390		T5	3		T14	1
all_values[0]	auto[0]	auto[1]	2141	1			T2	18		T14	2		T16	2
all_values[0]	auto[1]	auto[0]	100123245	1			T2	35868		T4	450		T14	221479
all_values[0]	auto[1]	auto[1]	507571	1			T2	456		T4	5		T14	580
all_values[1]	auto[0]	auto[0]	144871	1			T2	1603		T14	16		T16	4
all_values[1]	auto[0]	auto[1]	1636	1			T2	21		T14	10		T16	2
all_values[1]	auto[1]	auto[0]	100130645	1			T2	34655		T4	450		T5	3
all_values[1]	auto[1]	auto[1]	508076	1			T2	453		T4	5		T14	572
all_values[2]	auto[0]	auto[0]	149440	1			T2	1808		T14	1		T17	9
all_values[2]	auto[0]	auto[1]	1552	1			T2	15		T14	2		T17	7
all_values[2]	auto[1]	auto[0]	100126076	1			T2	34450		T4	450		T5	3
all_values[2]	auto[1]	auto[1]	508160	1			T2	459		T4	5		T14	580