Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
360742 |
1 |
|
|
T2 |
258 |
|
T4 |
2 |
|
T5 |
2 |
auto[1] |
332438 |
1 |
|
|
T2 |
444 |
|
T4 |
8 |
|
T14 |
778 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173245 |
1 |
|
|
T2 |
187 |
|
T14 |
180 |
|
T15 |
96 |
lower_val |
171177 |
1 |
|
|
T2 |
161 |
|
T4 |
1 |
|
T14 |
220 |
zero_val |
1818 |
1 |
|
|
T2 |
11 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
347152 |
1 |
|
|
T2 |
380 |
|
T4 |
2 |
|
T5 |
2 |
lower_val |
346022 |
1 |
|
|
T2 |
322 |
|
T4 |
8 |
|
T14 |
368 |
zero_val |
6 |
1 |
|
|
T155 |
2 |
|
T156 |
2 |
|
T157 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val , zero_val] |
[zero_val] |
* |
-- |
-- |
4 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45209 |
1 |
|
|
T2 |
32 |
|
T17 |
1 |
|
T82 |
1 |
higher_val |
higher_val |
auto[1] |
41544 |
1 |
|
|
T2 |
72 |
|
T14 |
84 |
|
T15 |
36 |
higher_val |
lower_val |
auto[0] |
45025 |
1 |
|
|
T2 |
29 |
|
T14 |
1 |
|
T83 |
19 |
higher_val |
lower_val |
auto[1] |
41464 |
1 |
|
|
T2 |
54 |
|
T14 |
95 |
|
T15 |
60 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T157 |
1 |
|
- |
- |
|
- |
- |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T155 |
2 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
44616 |
1 |
|
|
T2 |
33 |
|
T27 |
1 |
|
T83 |
15 |
lower_val |
higher_val |
auto[1] |
41110 |
1 |
|
|
T2 |
52 |
|
T14 |
119 |
|
T15 |
32 |
lower_val |
lower_val |
auto[0] |
44470 |
1 |
|
|
T2 |
28 |
|
T6 |
1 |
|
T83 |
21 |
lower_val |
lower_val |
auto[1] |
40981 |
1 |
|
|
T2 |
48 |
|
T4 |
1 |
|
T14 |
101 |
zero_val |
higher_val |
auto[0] |
678 |
1 |
|
|
T2 |
2 |
|
T5 |
1 |
|
T15 |
1 |
zero_val |
higher_val |
auto[1] |
248 |
1 |
|
|
T2 |
4 |
|
T17 |
1 |
|
T42 |
2 |
zero_val |
lower_val |
auto[0] |
672 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
220 |
1 |
|
|
T2 |
3 |
|
T17 |
3 |
|
T18 |
2 |